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mb/amd/birman: Enable PCIe RTD3 support 

Add PCIe RTD3 support so the NVMe gets placed into D3 when entering s0i3

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Fred Reitberger 2023-04-06 10:01:23 -04:00 committed by Felix Held
parent c706880bfe
commit 67bc6ab1e9
2 changed files with 15 additions and 2 deletions
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1
src/mainboard/amd/birman/Kconfig
View File

@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
select EC_ACPI select EC_ACPI
select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
select AMD_SOC_CONSOLE_UART if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select AMD_SOC_CONSOLE_UART if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
select DRIVERS_PCIE_RTD3_DEVICE
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select PCIEXP_ASPM select PCIEXP_ASPM
select PCIEXP_CLK_PM select PCIEXP_CLK_PM

16
src/mainboard/amd/birman/devicetree_phoenix.cb
View File

@ -162,12 +162,24 @@ chip soc/amd/phoenix
device domain 0 on device domain 0 on
device ref iommu on end device ref iommu on end
device ref gpp_bridge_1_1 on end # MXM device ref gpp_bridge_1_1 on end # MXM
device ref gpp_bridge_1_2 on end # NVMe SSD1 device ref gpp_bridge_1_2 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end # NVMe SSD1
device ref gpp_bridge_1_3 on end # GBE device ref gpp_bridge_1_3 on end # GBE
device ref gpp_bridge_2_1 on end # SD device ref gpp_bridge_2_1 on end # SD
device ref gpp_bridge_2_2 on end # WWAN device ref gpp_bridge_2_2 on end # WWAN
device ref gpp_bridge_2_3 on end # WIFI device ref gpp_bridge_2_3 on end # WIFI
device ref gpp_bridge_2_4 on end # NVMe SSD0 device ref gpp_bridge_2_4 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end # NVMe SSD0
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX) device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)