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siemens/mc_apl2: Activate TPM support 

The TPM chip is connected to the SPI interface of APL. The proper chip
select pin needs to be used in order to access the TPM in the memory
mapped space. This needed chip select is internally (inside APL)
routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to
make the TPM work on SPI bus.

TEST=Build coreboot for mc_apl2 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.

Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Mario Scheithauer 2019-01-28 16:18:45 +01:00 committed by Patrick Georgi
parent 1c105b0c8a
commit 67be491458
3 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig
View File

@ -6,5 +6,8 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVER_INTEL_I210 select DRIVER_INTEL_I210
select DRIVERS_I2C_RX6110SA select DRIVERS_I2C_RX6110SA
select DRIVER_SIEMENS_NC_FPGA select DRIVER_SIEMENS_NC_FPGA
select MAINBOARD_HAS_TPM2
select MAINBOARD_HAS_LPC_TPM
select TPM_ON_FAST_SPI
endif # BOARD_SIEMENS_MC_APL2 endif # BOARD_SIEMENS_MC_APL2

5
src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
View File

@ -104,6 +104,11 @@ chip soc/intel/apollolake
device pci 1d.0 off end # - UFS device pci 1d.0 off end # - UFS
device pci 1e.0 off end # - SDIO device pci 1e.0 off end # - SDIO
device pci 1f.0 on end # - LPC device pci 1f.0 on end # - LPC
device pci 1f.0 on # - LPC
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device pci 1f.1 on end # - SMBUS device pci 1f.1 on end # - SMBUS
end end
end end

4
src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
View File

@ -363,8 +363,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD),
/* SIO_SPI_FS0_1V8 - Connected to ESPI_CS0# of SMARC connector. */ /* SIO_SPI_FS0_1V8 - Connected to ESPI_CS0# of SMARC connector. */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, DN_20K, DEEP, NF1, HIZCRx0, ENPD), PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, DN_20K, DEEP, NF1, HIZCRx0, ENPD),
/* SIO_SPI_FS1_1V8 - Connected to ESPI_CS1# of SMARC connector. */ /* SIO_SPI_FS1_1V8 - Connected to FST_SPI_CS2_N of SMARC connector. */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx0, ENPD), PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),
/* SIO_SPI_MISO_1V8 - Connected to ESPI_IO_0 of SMARC connector. */ /* SIO_SPI_MISO_1V8 - Connected to ESPI_IO_0 of SMARC connector. */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, DN_20K, DEEP, NF1, HIZCRx0, ENPD), PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, DN_20K, DEEP, NF1, HIZCRx0, ENPD),
/* SIO_SPI_MOSI_1V8 - Connected to ESPI_IO_1 of SMARC connector. */ /* SIO_SPI_MOSI_1V8 - Connected to ESPI_IO_1 of SMARC connector. */