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soc/amd/common: Add DRAM clear option to northbridge.c 

AmdInitPost() can be instructed to clear DRAM after a reset or to
preserve it. Use SetMemParams() to tell AGESA which action to take.

Note that any overrides from OemPostParams (OemCustomize.c) are not
affected by this change.

Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Richard Spiegel 2017-11-09 16:04:35 -07:00 committed by Aaron Durbin
parent 185988234d
commit 67c2a7b487
4 changed files with 28 additions and 4 deletions
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11
src/soc/amd/common/agesawrapper.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
* Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -24,6 +24,7 @@
#include <BiosCallOuts.h>
#include <string.h>
void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {}
void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {}
#define FILECODE UNASSIGNED_FILE_FILECODE
@ -118,14 +119,18 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
// Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow
// the compiler to flag the error if CONFIG_GFXUMA is not set.
PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;
PostParams->MemConfig.UmaSize = 0;
PostParams->MemConfig.BottomIo = (UINT16)
(CONFIG_BOTTOMIO_POSITION >> 24);
SetMemParams(PostParams);
OemPostParams(PostParams);
printk(BIOS_SPEW, "DRAM clear on reset: %s\n",
(PostParams->MemConfig.EnableMemClr == FALSE) ? "Keep" :
(PostParams->MemConfig.EnableMemClr == TRUE) ? "Clear" :
"unknown"
);
status = AmdInitPost (PostParams);

3
src/soc/amd/common/agesawrapper.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -54,5 +54,6 @@ VOID amd_initcpuio(void);
const void *agesawrapper_locate_module(const CHAR8 name[8]);
void OemPostParams(AMD_POST_PARAMS *PostParams);
void SetMemParams(AMD_POST_PARAMS *PostParams);
#endif /* __AGESAWRAPPER_H__ */

4
src/soc/amd/stoneyridge/chip.h
View File

@ -24,6 +24,10 @@
struct soc_amd_stoneyridge_config {
u8 spdAddrLookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
enum {
DRAM_CONTENTS_KEEP,
DRAM_CONTENTS_CLEAR
} dram_clear_on_reset;
};
typedef struct soc_amd_stoneyridge_config config_t;

14
src/soc/amd/stoneyridge/romstage.c
View File

@ -111,3 +111,17 @@ asmlinkage void car_stage_entry(void)
post_code(0x50); /* Should never see this post code. */
}
void SetMemParams(AMD_POST_PARAMS *PostParams)
{
const struct soc_amd_stoneyridge_config *cfg;
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "ERROR: Could not find SoC devicetree config\n");
return;
}
cfg = dev->chip_info;
PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;
}