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ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields 

After the obsoletion of Processor() it is necessary to provide
_CST package to define P_LVLx IO addresses for C2/C3 transitions.
The latency values from _CST will always replace those in FADT.

Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kyösti Mälkki 2023-04-14 10:20:03 +03:00
parent 88fefd4feb
commit 67c48a3677
13 changed files with 4 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/acpi/acpi.c
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@ -1685,6 +1685,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
/* should be 0 ACPI 3.0 */
fadt->reserved = 0;
/* P_LVLx latencies are not used as CPU _CST will override them. */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->preferred_pm_profile = acpi_get_preferred_pm_profile();
if (CONFIG(USE_PC_CMOS_ALTCENTURY))

4
src/soc/amd/cezanne/acpi.c
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@ -69,10 +69,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fill_fadt_extended_pm_regs(fadt);
/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
overridden by the _CST packages in the processor devices. */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->century = RTC_ALT_CENTURY;
fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */

4
src/soc/amd/glinda/acpi.c
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@ -72,10 +72,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fill_fadt_extended_pm_regs(fadt);
/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
overridden by the _CST packages in the processor devices. */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->century = RTC_ALT_CENTURY;
fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */

4
src/soc/amd/mendocino/acpi.c
View File

@ -71,10 +71,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fill_fadt_extended_pm_regs(fadt);
/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
overridden by the _CST packages in the processor devices. */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->century = RTC_ALT_CENTURY;
fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */

4
src/soc/amd/phoenix/acpi.c
View File

@ -72,10 +72,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fill_fadt_extended_pm_regs(fadt);
/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
overridden by the _CST packages in the processor devices. */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->century = RTC_ALT_CENTURY;
fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */

4
src/soc/amd/picasso/acpi.c
View File

@ -77,10 +77,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fill_fadt_extended_pm_regs(fadt);
/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
overridden by the _CST packages in the processor devices. */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->day_alrm = RTC_DATE_ALARM;
fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */
fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */

4
src/soc/amd/stoneyridge/acpi.c
View File

@ -71,10 +71,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fill_fadt_extended_pm_regs(fadt);
/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
overridden by the _CST packages in the PSTATE SSDT. */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = RTC_DATE_ALARM;

2
src/soc/intel/xeon_sp/spr/soc_acpi.c
View File

@ -48,8 +48,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_blk = pmbase + PM2_CNT;
fadt->pm2_cnt_len = 1;
fadt->gpe0_blk = pmbase + 0x60;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1;
fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;

2
src/southbridge/amd/pi/hudson/fadt.c
View File

@ -44,8 +44,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4; /* 32 bits */
fadt->gpe0_blk_len = 8; /* 64 bits */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */

3
src/southbridge/intel/bd82x6x/fadt.c
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@ -31,9 +31,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
/* P_LVLx not used */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;

2
src/southbridge/intel/i82371eb/fadt.c
View File

@ -36,8 +36,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */

3
src/southbridge/intel/ibexpeak/fadt.c
View File

@ -31,9 +31,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
/* P_LVLx not used */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;

3
src/southbridge/intel/lynxpoint/fadt.c
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@ -44,9 +44,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
else
fadt->gpe0_blk_len = 2 * 8;
/* P_LVLx not used */
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 0;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;