GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/mancomb: Temporary fix to set eSPI mux 

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Eric Lai 2021-04-08 11:56:15 +08:00 committed by Martin Roth
parent 082be1073e
commit 67d099a7f2
1 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/mainboard/google/mancomb/bootblock.c
View File

@ -1,15 +1,37 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpimmio.h>
#include <bootblock_common.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
void bootblock_mainboard_early_init(void)
{
size_t num_gpios;
uint32_t dword;
const struct soc_amd_gpio *gpios;
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
gpios = variant_early_gpio_table(&num_gpios);
program_gpios(gpios, num_gpios);
}
printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
dword = pci_read_config32(SOC_LPC_DEV, 0x78);
dword &= 0xFFFFF9F3;
dword |= 0x200;
pci_write_config32(SOC_LPC_DEV, 0x78, dword);
pci_write_config32(SOC_LPC_DEV, 0x44, 0);
pci_write_config32(SOC_LPC_DEV, 0x48, 0);
dword = pm_read32(0x90);
dword |= 1 << 16;
pm_write32(0x90, dword);
dword = pm_read32(0x74);
dword |= 3 << 10;
pm_write32(0x74, dword);
}