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Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management" 

This reverts commit 287cc02c00.

Reason for revert: it will break s0ix.

BUG=b:201266532
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
David Wu 2021-11-01 12:14:03 +00:00 committed by Felix Held
parent 43cf27d3a7
commit 67d62fdfed
1 changed files with 0 additions and 11 deletions
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11
src/mainboard/google/brya/variants/kano/overridetree.cb
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@ -15,17 +15,6 @@ end
chip soc/intel/alderlake chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
# This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify
# the minimum PCH IRQ pulse width with Intel, b/180111628
register "gpio_override_pm" = "1"
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0"
# FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented. # bypass rails implemented.
register "ext_fivr_settings" = "{ register "ext_fivr_settings" = "{