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soc/intel/broadwell: Sort SA registers in ascending order 

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46337
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-13 13:47:00 +02:00
parent ffc505b995
commit 67e1d359de
1 changed files with 24 additions and 17 deletions
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41
src/soc/intel/broadwell/include/soc/systemagent.h
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@ -29,8 +29,6 @@
#define EPBAR 0x40 #define EPBAR 0x40
#define MCHBAR 0x48 #define MCHBAR 0x48
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define GGC 0x50 /* GMCH Graphics Control */ #define GGC 0x50 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */ #define DEVEN 0x54 /* Device Enable */
#define DEVEN_D7EN (1 << 14) #define DEVEN_D7EN (1 << 14)
@ -45,6 +43,11 @@
#define DPR_EPM (1 << 2) #define DPR_EPM (1 << 2)
#define DPR_PRS (1 << 1) #define DPR_PRS (1 << 1)
#define DPR_SIZE_MASK 0xff0 #define DPR_SIZE_MASK 0xff0
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define MESEG_BASE 0x70 /* Management Engine Base. */
#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
#define PAM0 0x80 #define PAM0 0x80
#define PAM1 0x81 #define PAM1 0x81
@ -60,14 +63,7 @@
#define D_LCK (1 << 4) #define D_LCK (1 << 4)
#define G_SMRAME (1 << 3) #define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define CAPID0_A 0xe4
#define VTD_DISABLE (1 << 23)
#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
#define DMAR_LCKDN (1 << 31)
#define PRSCAPDIS (1 << 2)
#define MESEG_BASE 0x70 /* Management Engine Base. */
#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
#define REMAPBASE 0x90 /* Remap base. */ #define REMAPBASE 0x90 /* Remap base. */
#define REMAPLIMIT 0x98 /* Remap limit. */ #define REMAPLIMIT 0x98 /* Remap limit. */
#define TOM 0xa0 /* Top of DRAM in memory controller space. */ #define TOM 0xa0 /* Top of DRAM in memory controller space. */
@ -78,6 +74,13 @@
#define TOLUD 0xbc /* Top of Low Used Memory */ #define TOLUD 0xbc /* Top of Low Used Memory */
#define SKPAD 0xdc /* Scratchpad Data */ #define SKPAD 0xdc /* Scratchpad Data */
#define CAPID0_A 0xe4
#define VTD_DISABLE (1 << 23)
#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
#define DMAR_LCKDN (1 << 31)
#define PRSCAPDIS (1 << 2)
/* MCHBAR */ /* MCHBAR */
#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x)))
@ -85,20 +88,23 @@
#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) #define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x)))
#define MCHBAR_PEI_VERSION 0x5034 #define MCHBAR_PEI_VERSION 0x5034
#define BIOS_RESET_CPL 0x5da8
#define GFXVTBAR 0x5400 #define GFXVTBAR 0x5400
#define EDRAMBAR 0x5408 #define EDRAMBAR 0x5408
#define VTVC0BAR 0x5410 #define VTVC0BAR 0x5410
#define MCH_PAIR 0x5418 #define MCH_PAIR 0x5418
#define GDXCBAR 0x5420 #define GDXCBAR 0x5420
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define MCH_PKG_POWER_LIMIT_HI 0x59a4
#define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_LO 0x58e0
#define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define MCH_DDR_POWER_LIMIT_HI 0x58e4
/* PCODE MMIO communications live in the MCHBAR. */ #define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define BIOS_MAILBOX_INTERFACE 0x5da4 #define MCH_PKG_POWER_LIMIT_HI 0x59a4
/* PCODE MMIO communications live in the MCHBAR */
#define BIOS_MAILBOX_DATA 0x5da0
#define BIOS_MAILBOX_INTERFACE 0x5da4
#define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_RUN_BUSY (1 << 31)
#define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_READ_PCS 1
#define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_WRITE_PCS 2
@ -108,7 +114,8 @@
#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26
#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27
/* Errors are returned back in bits 7:0. */
/* Errors are returned back in bits 7:0 */
#define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_NONE 0
#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
#define MAILBOX_BIOS_ERROR_TIMEOUT 2 #define MAILBOX_BIOS_ERROR_TIMEOUT 2
@ -117,8 +124,8 @@
#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
#define MAILBOX_BIOS_ERROR_VR_ERROR 7 #define MAILBOX_BIOS_ERROR_VR_ERROR 7
/* Data is passed through bits 31:0 of the data register. */
#define BIOS_MAILBOX_DATA 0x5da0 #define BIOS_RESET_CPL 0x5da8
/* System Agent identification */ /* System Agent identification */
u8 systemagent_revision(void); u8 systemagent_revision(void);