soc/amd/mendocino: Force resets to be cold

Like Cezanne, Mendocino does not support warm resets. Change all resets
(including resets in the OS) to cold resets (like Cezanne).

BUG=b:248221908
TEST=Run suspend_stress_test, then reboot

Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72486
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>

src/soc/amd/mendocino/fch.c

@@ -126,6 +126,11 @@ static void fch_init_acpi_ports(void)
 				PM_ACPI_TIMER_EN_EN);
 }
 
+static void fch_init_resets(void)
+{
+	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
+}
+
 /* configure the general purpose PCIe clock outputs according to the devicetree settings */
 static void gpp_clk_setup(void)
 {
@@ -197,6 +202,7 @@ static void cgpll_clock_gate_init(void)
 
 void fch_init(void *chip_info)
 {
+	fch_init_resets();
 	i2c_soc_init();
 	fch_init_acpi_ports();
 

src/soc/amd/mendocino/reset.c

@@ -17,8 +17,8 @@ void do_cold_reset(void)
 
 void do_warm_reset(void)
 {
-	/* Assert reset signals only. */
-	outb(RST_CPU | SYS_RST, RST_CNT);
+	/* Warm resets are not supported and must be executed as cold */
+	do_cold_reset();
 }
 
 void do_board_reset(void)