soc/intel/cannonlake: Add PCIE IRQs
Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Bora Guvendik
Aaron Durbin
parent
a0e0b054bd
commit
67fb347668
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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* (Written by Bora Guvendik <bora.guvendik@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
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Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
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Name (_SEG, Zero) // _SEG: PCI Segment
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Name (_ADR, Zero) // _ADR: Address
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Name (_UID, Zero) // _UID: Unique ID
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_PRT)
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{
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Return(Package() {
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// PCI Bridge
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// cAVS, SMBus, GbE, Nothpeak
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Package(){0x001FFFFF, 0, 0, 16 },
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Package(){0x001FFFFF, 1, 0, 17 },
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Package(){0x001FFFFF, 2, 0, 18 },
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Package(){0x001FFFFF, 3, 0, 19 },
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// SerialIo and SCS
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Package(){0x001EFFFF, 0, 0, 20 },
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Package(){0x001EFFFF, 1, 0, 21 },
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Package(){0x001EFFFF, 2, 0, 22 },
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Package(){0x001EFFFF, 3, 0, 23 },
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// PCI Express Port 9-16
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Package(){0x001DFFFF, 0, 0, 16 },
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Package(){0x001DFFFF, 1, 0, 17 },
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Package(){0x001DFFFF, 2, 0, 18 },
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Package(){0x001DFFFF, 3, 0, 19 },
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// PCI Express Port 1-8
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Package(){0x001CFFFF, 0, 0, 16 },
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Package(){0x001CFFFF, 1, 0, 17 },
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Package(){0x001CFFFF, 2, 0, 18 },
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Package(){0x001CFFFF, 3, 0, 19 },
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// PCI Express Port 17-20
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Package(){0x001BFFFF, 0, 0, 16 },
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Package(){0x001BFFFF, 1, 0, 17 },
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Package(){0x001BFFFF, 2, 0, 18 },
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Package(){0x001BFFFF, 3, 0, 19 },
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// eMMC
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Package(){0x001AFFFF, 0, 0, 16 },
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Package(){0x001AFFFF, 1, 0, 17 },
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Package(){0x001AFFFF, 2, 0, 18 },
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Package(){0x001AFFFF, 3, 0, 19 },
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// SerialIo
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Package(){0x0019FFFF, 0, 0, 32 },
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Package(){0x0019FFFF, 1, 0, 33 },
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Package(){0x0019FFFF, 2, 0, 34 },
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// SATA controller
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Package(){0x0017FFFF, 0, 0, 16 },
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// CSME (HECI, IDE-R, Keyboard and Text redirection
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Package(){0x0016FFFF, 0, 0, 16 },
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Package(){0x0016FFFF, 1, 0, 17 },
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Package(){0x0016FFFF, 2, 0, 18 },
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Package(){0x0016FFFF, 3, 0, 19 },
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// SerialIo
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Package(){0x0015FFFF, 0, 0, 16 },
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Package(){0x0015FFFF, 1, 0, 17 },
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Package(){0x0015FFFF, 2, 0, 18 },
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Package(){0x0015FFFF, 3, 0, 19 },
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// CNL: D20: xHCI, OTG, CNVi WiFi, SDcard
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Package(){0x0014FFFF, 0, 0, 16 },
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Package(){0x0014FFFF, 1, 0, 17 },
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Package(){0x0014FFFF, 2, 0, 18 },
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Package(){0x0014FFFF, 3, 0, 19 },
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// Integrated Sensor Hub
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Package(){0x0013FFFF, 0, 0, 20 },
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// Thermal, UFS, SerialIo SPI 2
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Package(){0x0012FFFF, 0, 0, 16 },
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Package(){0x0012FFFF, 1, 0, 24 },
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Package(){0x0012FFFF, 2, 0, 18 },
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Package(){0x0012FFFF, 3, 0, 19 },
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// Host Bridge
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// Root Port D1F0
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Package(){0x0001FFFF, 0, 0, 16 },
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Package(){0x0001FFFF, 1, 0, 17 },
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Package(){0x0001FFFF, 2, 0, 18 },
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Package(){0x0001FFFF, 3, 0, 19 },
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// Root Port D1F1
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// Root Port D1F2
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// IGFX Device
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Package(){0x0002FFFF, 0, 0, 16 },
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// Thermal Device
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Package(){0x0004FFFF, 0, 0, 16 },
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// IPU Device
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Package(){0x0005FFFF, 0, 0, 16 },
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// GNA Device
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Package(){0x0008FFFF, 0, 0, 16 },
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})
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}
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@ -0,0 +1,20 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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* (Written by Bora Guvendik <bora.guvendik@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* PCI IRQ assignment */
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#include "pci_irqs.asl"
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