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drivers/intel/gma: fix opregion SCI register for Atom platforms 

Most Intel platforms use separate registers for software-based
SMI (0xe0) and SCI (0xe8), but Atom-based platforms use a single
combined register (0xe0) for both. Adjust opregion implementation
to use the correct register for Atom-based platforms.

Test: Boot Windows on Atom-based ChromeOS device with Tianocore
payload and non-VBIOS graphics init; observe Intel display
driver loaded correctly and internal display not blank.
(requires additional change for Atom platforms to select
CONFIG_INTEL_GMA_SWSMISCI)

Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Matt DeVillier 2018-02-11 01:17:01 -06:00 committed by Patrick Georgi
parent 3ab36b84f7
commit 681ef51d73
3 changed files with 20 additions and 2 deletions
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7
src/drivers/intel/gma/Kconfig
View File

@ -47,6 +47,13 @@ config INTEL_GMA_SSC_ALTERNATE_REF
supported platform with a choice seems to be Pineview, where the
alternative is 100MHz vs. the default 96MHz.
config INTEL_GMA_SWSMISCI
bool
default n
help
Select this option for Atom-based platforms which use the SWSMISCI
register (0xe0) rather than the SWSCI register (0xe8).
config GFX_GMA_ANALOG_I2C_HDMI_B
bool

14
src/drivers/intel/gma/opregion.c
View File

@ -32,6 +32,7 @@ void intel_gma_opregion_register(uintptr_t opregion)
{
device_t igd;
u16 reg16;
u16 sci_reg;
igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
if (!igd || !igd->enabled)
@ -43,15 +44,24 @@ void intel_gma_opregion_register(uintptr_t opregion)
*/
pci_write_config32(igd, ASLS, opregion);
/*
* Atom-based platforms use a combined SMI/SCI register,
* whereas non-Atom platforms use a separate SCI register.
*/
if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
sci_reg = SWSMISCI;
else
sci_reg = SWSCI;
/*
* Intel's Windows driver relies on this:
* Intel BIOS Specification
* Chapter 5.4 "ASL Software SCI Handler"
*/
reg16 = pci_read_config16(igd, SWSCI);
reg16 = pci_read_config16(igd, sci_reg);
reg16 &= ~GSSCIE;
reg16 |= SMISCISEL;
pci_write_config16(igd, SWSCI, reg16);
pci_write_config16(igd, sci_reg, reg16);
}
/* Restore ASLS register on S3 resume and prepare SWSCI. */

1
src/drivers/intel/gma/opregion.h
View File

@ -25,6 +25,7 @@
/* IGD PCI Configuration register */
#define ASLS 0xfc /* OpRegion Base */
#define SWSCI 0xe8 /* SWSCI Register */
#define SWSMISCI 0xe0 /* SWSMISCI Register */
#define GSSCIE (1 << 0) /* SCI Event trigger */
#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */