sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()

This adds delivery of PIC/i8259 interrupts via ExtNMI on the
affected platfoms.

Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/soc/intel/broadwell/pch/lpc.c

@@ -33,7 +33,7 @@ static void pch_enable_ioapic(struct device *dev)
 	/* PCH-LP has 40 redirection entries */
 	ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 }
 
 static void enable_hpet(struct device *dev)

src/soc/intel/common/block/lpc/lpc_lib.c

@@ -283,7 +283,7 @@ void pch_enable_ioapic(void)
 	/* affirm full set of redirection table entries ("write once") */
 	ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
 
-	set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
+	setup_ioapic((void *)IO_APIC_ADDR, 0x02);
 }
 
 static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {

src/soc/intel/denverton_ns/lpc.c

@@ -34,7 +34,7 @@ static void pch_enable_ioapic(struct device *dev)
 	/* affirm full set of redirection table entries ("write once") */
 	ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
 
-	set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0);
+	setup_ioapic((void *)IO_APIC_ADDR, IO_APIC0);
 }
 
 /* interrupt router lookup for internal devices */

src/southbridge/intel/bd82x6x/lpc.c

@@ -44,7 +44,7 @@ static void pch_enable_ioapic(struct device *dev)
 	/* affirm full set of redirection table entries ("write once") */
 	ioapic_lock_max_vectors(VIO_APIC_VADDR);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 }
 
 static void pch_enable_serial_irqs(struct device *dev)

src/southbridge/intel/i82371eb/isa.c

@@ -61,7 +61,7 @@ static void isa_init(struct device *dev)
 		pci_write_config16(dev, XBCS, reg16);
 
 		/* Set and verify the IOAPIC ID. */
-		set_ioapic_id(VIO_APIC_VADDR, ioapic_id);
+		setup_ioapic(VIO_APIC_VADDR, ioapic_id);
 		if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR))
 			die("IOAPIC error!\n");
 	}

src/southbridge/intel/i82801dx/lpc.c

@@ -48,7 +48,7 @@ static void i82801dx_enable_ioapic(struct device *dev)
 	pci_write_config32(dev, GEN_CNTL, reg32);
 	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 
 	ioapic_set_boot_config(VIO_APIC_VADDR, true);
 }

src/southbridge/intel/i82801gx/lpc.c

@@ -33,7 +33,7 @@
  */
 static void i82801gx_enable_ioapic(struct device *dev)
 {
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 }
 
 static void i82801gx_enable_serial_irqs(struct device *dev)

src/southbridge/intel/ibexpeak/lpc.c

@@ -37,7 +37,7 @@ static void pch_enable_ioapic(struct device *dev)
 	/* affirm full set of redirection table entries ("write once") */
 	ioapic_lock_max_vectors(VIO_APIC_VADDR);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x01);
+	setup_ioapic(VIO_APIC_VADDR, 0x01);
 }
 
 static void pch_enable_serial_irqs(struct device *dev)

src/southbridge/intel/lynxpoint/lpc.c

@@ -42,7 +42,7 @@ static void pch_enable_ioapic(struct device *dev)
 	else
 		ioapic_lock_max_vectors(VIO_APIC_VADDR);
 
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+	setup_ioapic(VIO_APIC_VADDR, 0x02);
 
 }