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soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 

In x86 processor as per Software Developer's manual there are 2 ways to
get CPU topology by querying the processor. BIOS can use CPUID
instruction using CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) as input or
CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) as an input. Both will return
valid CPU topology data.

While CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) returns data related to number
of threads, core and package, CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F)
provides more granular information regarding Die, package etc.

coreboot uses V2 to in order to query and return CPU topology data as of
now since that's the highest instruction of CPUID which is supported,
there is a mismatch in the way FSP processes the data.

FSP queries coreboot MP services to get CPU topology data which uses
structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or
CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since coreboot returns V2 data in
structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there
is hang observed on ADL_N CPUs.

To solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY
data to processor_info_buffer->Location structure so remove use of
CPUID_EXTENDED_CPU_TOPOLOGY_V2

Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202
Files:
MdePkg/Include/Protocol/MpService.h#L182
UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127
UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120
Ref doc: Software Developer’s Manual volume 3 CH 8.9

BUG=b:220652104
TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology
value and observe system boots (no hang).

Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Ronak Kanabar 2022-02-24 10:09:29 +05:30 committed by Felix Held
parent f5c2f253a7
commit 68305aa3b0
1 changed files with 1 additions and 6 deletions
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5
src/soc/intel/common/block/cpu/cpulib.c
View File

@ -13,7 +13,6 @@
#include <types.h>
#define CPUID_EXTENDED_CPU_TOPOLOGY 0x0b
#define CPUID_EXTENDED_CPU_TOPOLOGY_V2 0x1f
#define LEVEL_TYPE_CORE 2
#define LEVEL_TYPE_SMT 1
@ -443,10 +442,6 @@ static void get_cpu_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits)
/* Assert if extended CPU topology not supported */
assert(cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY);
/* Check for extended CPU topology CPUID support */
if (cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY_V2)
cpu_id_op = CPUID_EXTENDED_CPU_TOPOLOGY_V2;
else if (cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY)
cpu_id_op = CPUID_EXTENDED_CPU_TOPOLOGY;
*core_bits = level_num = 0;