soc/intel/apollolake: Fix space between type, * and variable name
Fix the following errors detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" TEST=Build for reef Change-Id: I4a762d8fa762057a06e601dfed10538adc5d8bc8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18719 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -81,7 +81,7 @@ unsigned long acpi_fill_madt(unsigned long current)
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return acpi_madt_irq_overrides(current);
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return acpi_madt_irq_overrides(current);
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}
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}
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void acpi_fill_fadt(acpi_fadt_t * fadt)
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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{
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const uint16_t pmbase = ACPI_PMIO_BASE;
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const uint16_t pmbase = ACPI_PMIO_BASE;
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@ -116,7 +116,7 @@ static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data,
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len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
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/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
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memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len);
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memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len);
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}
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}
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/* Drain FDATAn FIFO after a read transaction populates data. */
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/* Drain FDATAn FIFO after a read transaction populates data. */
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@ -125,7 +125,7 @@ static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len)
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len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
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/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
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memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len);
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memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len);
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}
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}
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/* Fire up a transfer using the hardware sequencer. */
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/* Fire up a transfer using the hardware sequencer. */
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@ -177,7 +177,7 @@ void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
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gpio_configure_pad(cfg + i);
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gpio_configure_pad(cfg + i);
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}
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}
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void * gpio_dwx_address(const uint16_t pad)
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void *gpio_dwx_address(const uint16_t pad)
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{
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{
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/* Calculate Address of DW0 register for given GPIO
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/* Calculate Address of DW0 register for given GPIO
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* pad - GPIO number
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* pad - GPIO number
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@ -161,7 +161,7 @@ void gpio_configure_pad(const struct pad_config *cfg);
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void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
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void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
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/* Calculate GPIO DW0 address */
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/* Calculate GPIO DW0 address */
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void * gpio_dwx_address(const uint16_t pad);
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void *gpio_dwx_address(const uint16_t pad);
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/*
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/*
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* Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
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* Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
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* are passed which is then mapped to proper groups for MISCCFG. This basically
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* are passed which is then mapped to proper groups for MISCCFG. This basically
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@ -24,7 +24,7 @@
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#define RTC_CONFIG 0x3400
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#define RTC_CONFIG 0x3400
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#define RTC_CONFIG_UCMOS_ENABLE (1 << 2)
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#define RTC_CONFIG_UCMOS_ENABLE (1 << 2)
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static inline void * iosf_address(uint16_t port, uint16_t reg)
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static inline void *iosf_address(uint16_t port, uint16_t reg)
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{
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{
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uintptr_t addr = (CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3));
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uintptr_t addr = (CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3));
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return (void *)addr;
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return (void *)addr;
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