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mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp 

This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.

BUG=none
TEST=Tested that eDP & DP works on WHLRVP

Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
sridhar 2019-06-13 14:26:00 +05:30 committed by Martin Roth
parent ba5f318736
commit 685b377e7e
1 changed files with 13 additions and 0 deletions
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13
src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
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@ -9,6 +9,19 @@ chip soc/intel/cannonlake
register "ScsEmmcHs400Enabled" = "1"
register "HeciEnabled" = "1"
# Enable eDP device
register "DdiPortEdp" = "1"
# Enable HPD for DDI ports B/C/D/F
register "DdiPortBHpd" = "1"
register "DdiPortCHpd" = "1"
register "DdiPortDHpd" = "1"
register "DdiPortFHpd" = "1"
# Enable DDC for DDI ports B/C/D/F
register "DdiPortBDdc" = "1"
register "DdiPortCDdc" = "1"
register "DdiPortDDdc" = "1"
register "DdiPortFDdc" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"