sb/intel/ibexpeak: Drop P_LVLx support in FADT
IO MWAIT redirection is not enabled. The code is missing, but C-states should instead be reported using the _CST ACPI object. Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -49,7 +49,6 @@ chip northbridge/intel/ironlake
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register "gen3_dec" = "0x1c1681" # EC ?
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register "gen4_dec" = "0x040069" # ?
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register "c2_latency" = "1"
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register "docking_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
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@ -49,7 +49,6 @@ chip northbridge/intel/ironlake
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register "gen3_dec" = "0x1c1681"
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register "gen4_dec" = "0x040069"
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register "c2_latency" = "1"
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register "docking_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
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@ -11,7 +11,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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struct device *dev = pcidev_on_root(0x1f, 0);
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struct southbridge_intel_ibexpeak_config *chip = dev->chip_info;
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u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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int c2_latency;
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fadt->sci_int = 0x9;
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@ -32,12 +31,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 16;
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c2_latency = chip->c2_latency;
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if (!c2_latency) {
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c2_latency = 101; /* c2 unsupported */
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}
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fadt->p_lvl2_lat = c2_latency;
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fadt->p_lvl3_lat = 87;
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/* P_LVLx not used */
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fadt->p_lvl2_lat = 101;
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fadt->p_lvl3_lat = 1001;
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/* P_CNT not supported */
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fadt->duty_offset = 0;
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fadt->duty_width = 0;
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@ -54,9 +50,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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if (chip->docking_supported) {
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fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
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}
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if (c2_latency < 100) {
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fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
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}
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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