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sb/intel/ibexpeak: Drop P_LVLx support in FADT 

IO MWAIT redirection is not enabled. The code is missing, but C-states
should instead be reported using the _CST ACPI object.

Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2021-06-04 12:54:00 +02:00 committed by Patrick Georgi
parent 772c09739e
commit 685dc56b9f
3 changed files with 3 additions and 12 deletions
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1
src/mainboard/lenovo/t410/devicetree.cb
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@ -49,7 +49,6 @@ chip northbridge/intel/ironlake
register "gen3_dec" = "0x1c1681" # EC ? register "gen3_dec" = "0x1c1681" # EC ?
register "gen4_dec" = "0x040069" # ? register "gen4_dec" = "0x040069" # ?
register "c2_latency" = "1"
register "docking_supported" = "1" register "docking_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"

1
src/mainboard/lenovo/x201/devicetree.cb
View File

@ -49,7 +49,6 @@ chip northbridge/intel/ironlake
register "gen3_dec" = "0x1c1681" register "gen3_dec" = "0x1c1681"
register "gen4_dec" = "0x040069" register "gen4_dec" = "0x040069"
register "c2_latency" = "1"
register "docking_supported" = "1" register "docking_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"

13
src/southbridge/intel/ibexpeak/fadt.c
View File

@ -11,7 +11,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
struct device *dev = pcidev_on_root(0x1f, 0); struct device *dev = pcidev_on_root(0x1f, 0);
struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; struct southbridge_intel_ibexpeak_config *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
int c2_latency;
fadt->sci_int = 0x9; fadt->sci_int = 0x9;
@ -32,12 +31,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1; fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4; fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16; fadt->gpe0_blk_len = 16;
c2_latency = chip->c2_latency; /* P_LVLx not used */
if (!c2_latency) { fadt->p_lvl2_lat = 101;
c2_latency = 101; /* c2 unsupported */ fadt->p_lvl3_lat = 1001;
}
fadt->p_lvl2_lat = c2_latency;
fadt->p_lvl3_lat = 87;
/* P_CNT not supported */ /* P_CNT not supported */
fadt->duty_offset = 0; fadt->duty_offset = 0;
fadt->duty_width = 0; fadt->duty_width = 0;
@ -54,9 +50,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
if (chip->docking_supported) { if (chip->docking_supported) {
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
} }
if (c2_latency < 100) {
fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
}
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_width = 32;