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soc/amd/sabrina: Modify start address of PSP verstage 

PSP verstage can start at address 0 and use 200KB of PSP SRAM for
execution. Modify both the PSP SRAM start address and size for use by
PSP verstage.

BUG=b:220848544
TEST=Build Skyrim BIOS image with PSP verstage enabled.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73e13b82faa0f443570a0c839e7699a79bdae024
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2022-04-19 14:48:43 -06:00 committed by Felix Held
parent 43f51a041d
commit 685f123852
1 changed files with 5 additions and 5 deletions
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10
src/soc/amd/sabrina/include/soc/psp_verstage_addr.h
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@ -6,12 +6,12 @@
#define AMD_SABRINA_PSP_VERSTAGE_ADDR_H #define AMD_SABRINA_PSP_VERSTAGE_ADDR_H
/* /*
* Start of available space is 0x36000 and this is where the * Start of available space is 0x0 and this is where the
* header for the user app (verstage) must be mapped. * header for the user app (verstage) must be mapped.
* Size is 0x14000 bytes * Size is 208KB
*/ */
#define PSP_SRAM_START 0x26000 #define PSP_SRAM_START 0x0
#define PSP_SRAM_SIZE (148K) #define PSP_SRAM_SIZE (208K)
#define VERSTAGE_START PSP_SRAM_START #define VERSTAGE_START PSP_SRAM_START
/* /*
@ -19,7 +19,7 @@
* and make the size a multiple of 4k * and make the size a multiple of 4k
*/ */
#define PSP_VERSTAGE_STACK_START 0x41000 #define PSP_VERSTAGE_STACK_START 0x2a000
#define PSP_VERSTAGE_STACK_SIZE (40K) #define PSP_VERSTAGE_STACK_SIZE (40K)
#endif /* AMD_SABRINA_PSP_VERSTAGE_ADDR_H */ #endif /* AMD_SABRINA_PSP_VERSTAGE_ADDR_H */