mb/system76/rpl: Add Darter Pro 9 as a variant
The Darter Pro 9 (darp9) is a Raptor Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots with 5200 MT/s memory - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Change-Id: If19caa90e5f90939b2946392da343b7f91f568ca Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75278 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Crawford
Felix Held
parent
d7a07c2873
commit
6875231472
|
|
@ -210,6 +210,7 @@ The boards in this section are not real mainboards, but emulators.
|
|||
- [Darter Pro 6](system76/darp6.md)
|
||||
- [Darter Pro 7](system76/darp7.md)
|
||||
- [Darter Pro 8](system76/darp8.md)
|
||||
- [Darter Pro 9](system76/darp9.md)
|
||||
- [Galago Pro 4](system76/galp4.md)
|
||||
- [Galago Pro 5](system76/galp5.md)
|
||||
- [Galago Pro 6](system76/galp6.md)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
# Syste76 Darter Pro 9 (darp9)
|
||||
|
||||
## Specs
|
||||
|
||||
- CPU
|
||||
- Intel Core i5-1340P
|
||||
- Intel Core i7-1360P
|
||||
- EC
|
||||
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
|
||||
- Graphics
|
||||
- Intel Iris Xe Graphics
|
||||
- eDP 15.6" 1920x1080@60Hz LCD
|
||||
- 1x HDMI
|
||||
- 1x DisplayPort 1.4 over USB-C
|
||||
- Memory
|
||||
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
|
||||
- Networking
|
||||
- Gigabit Ethernet (Realtek RTL8111H)
|
||||
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6E AX210/211)
|
||||
- Power
|
||||
- 90W (19V, 4.74A) AC barrel adapter
|
||||
- USB-C charging, compatible with 65W+ chargers
|
||||
- 73Wh 4-cell Lithium-ion battery (L140BAT-4)
|
||||
- Sound
|
||||
- Realtek ALC256 codec
|
||||
- Internal speakers and microphone
|
||||
- Combined 3.5mm headphone/microphone jack
|
||||
- HDMI, USB-C DisplayPort audio
|
||||
- Storage
|
||||
- 2x M.2 PCIe NVMe Gen 4 SSDs
|
||||
- MicroSD card reader (OZ711LV2)
|
||||
- USB
|
||||
- 1x USB Type-C with Thunderbolt 4
|
||||
- 1x USB 3.2 Gen 2 Type-C
|
||||
- 1x USB 3.2 Gen 2 Type-A
|
||||
- 1x USB 2.0 Type-A
|
||||
- Dimensions
|
||||
- 35.7cm x 22.05cm x 1.99cm, 1.74kg
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+---------------------+
|
||||
| Type | Value |
|
||||
+=====================+=====================+
|
||||
| Socketed flash | no |
|
||||
+---------------------+---------------------+
|
||||
| Vendor | GigaDevice |
|
||||
+---------------------+---------------------+
|
||||
| Model | GD25B256E |
|
||||
+---------------------+---------------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+---------------------+
|
||||
| Package | WSON-8 |
|
||||
+---------------------+---------------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
```
|
||||
|
||||
The flash chip (U22) is above the left DIMM slot.
|
||||
|
|
@ -30,6 +30,11 @@ config BOARD_SYSTEM76_ADDW3
|
|||
select PCIEXP_HOTPLUG
|
||||
select SOC_INTEL_ALDERLAKE_PCH_S
|
||||
|
||||
config BOARD_SYSTEM76_DARP9
|
||||
select BOARD_SYSTEM76_RPL_COMMON
|
||||
select PCIEXP_HOTPLUG
|
||||
select SOC_INTEL_ALDERLAKE_PCH_P
|
||||
|
||||
config BOARD_SYSTEM76_GAZE18
|
||||
select BOARD_SYSTEM76_RPL_COMMON
|
||||
select EC_SYSTEM76_EC_COLOR_KEYBOARD
|
||||
|
|
@ -56,6 +61,7 @@ config MAINBOARD_DIR
|
|||
|
||||
config VARIANT_DIR
|
||||
default "addw3" if BOARD_SYSTEM76_ADDW3
|
||||
default "darp9" if BOARD_SYSTEM76_DARP9
|
||||
default "gaze18" if BOARD_SYSTEM76_GAZE18
|
||||
default "oryp11" if BOARD_SYSTEM76_ORYP11
|
||||
default "serw13" if BOARD_SYSTEM76_SERW13
|
||||
|
|
@ -65,18 +71,21 @@ config OVERRIDE_DEVICETREE
|
|||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "addw3" if BOARD_SYSTEM76_ADDW3
|
||||
default "darp9" if BOARD_SYSTEM76_DARP9
|
||||
default "gaze18" if BOARD_SYSTEM76_GAZE18
|
||||
default "oryp11" if BOARD_SYSTEM76_ORYP11
|
||||
default "serw13" if BOARD_SYSTEM76_SERW13
|
||||
|
||||
config MAINBOARD_SMBIOS_PRODUCT_NAME
|
||||
default "Adder WS" if BOARD_SYSTEM76_ADDW3
|
||||
default "Darter Pro" if BOARD_SYSTEM76_DARP9
|
||||
default "Gazelle" if BOARD_SYSTEM76_GAZE18
|
||||
default "Oryx Pro" if BOARD_SYSTEM76_ORYP11
|
||||
default "Serval WS" if BOARD_SYSTEM76_SERW13
|
||||
|
||||
config MAINBOARD_VERSION
|
||||
default "addw3" if BOARD_SYSTEM76_ADDW3
|
||||
default "darp9" if BOARD_SYSTEM76_DARP9
|
||||
default "gaze18" if BOARD_SYSTEM76_GAZE18
|
||||
default "oryp11" if BOARD_SYSTEM76_ORYP11
|
||||
default "serw13" if BOARD_SYSTEM76_SERW13
|
||||
|
|
|
|||
|
|
@ -1,6 +1,9 @@
|
|||
config BOARD_SYSTEM76_ADDW3
|
||||
bool "addw3"
|
||||
|
||||
config BOARD_SYSTEM76_DARP9
|
||||
bool "darp9"
|
||||
|
||||
config BOARD_SYSTEM76_GAZE18
|
||||
bool "gaze18"
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
FLASH 32M {
|
||||
SI_DESC 4K
|
||||
SI_ME 4824K
|
||||
SI_BIOS@16M 16M {
|
||||
RW_MRC_CACHE 64K
|
||||
SMMSTORE(PRESERVE) 256K
|
||||
WP_RO {
|
||||
FMAP 4K
|
||||
COREBOOT(CBFS)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
Board name: darp9
|
||||
Release year: 2023
|
||||
Binary file not shown.
|
|
@ -0,0 +1,227 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKE#
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
|
||||
PAD_NC(GPD7, NONE),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
|
||||
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
|
||||
PAD_NC(GPP_A6, NONE),
|
||||
PAD_NC(GPP_A7, NONE), // SATAGP0_PCIE_SSD2
|
||||
PAD_CFG_GPO(GPP_A8, 1, PLTRST), // GPIO_LANRTD3
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_NC(GPP_A12, NONE), // SATAGP1_SATA_SSD1
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
// GPP_A16 missing
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE), // SSD1_PCIE_WAKE#
|
||||
PAD_NC(GPP_A22, NONE), // SSD2_PCIE_WAKE#
|
||||
PAD_NC(GPP_A23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
|
||||
PAD_NC(GPP_B2, NONE),
|
||||
PAD_CFG_GPO(GPP_B3, 0, DEEP), // SCI#
|
||||
PAD_CFG_GPO(GPP_B4, 0, DEEP), // SWI#
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
// GPP_B9 missing
|
||||
// GPP_B10 missing
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
PAD_CFG_GPO(GPP_B16, 1, PLTRST), // M2_SSD1_RST#
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST#_R
|
||||
PAD_NC(GPP_B18, NONE), // NO REBOOT strap
|
||||
// GPP_B19 missing
|
||||
// GPP_B20 missing
|
||||
// GPP_B21 missing
|
||||
// GPP_B22 missing
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR; XXX: NC?
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR; XXX: NC?
|
||||
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK_R
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA_R
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
|
||||
// GPP_C8 missing
|
||||
// GPP_C9 missing
|
||||
// GPP_C10 missing
|
||||
// GPP_C11 missing
|
||||
// GPP_C12 missing
|
||||
// GPP_C13 missing
|
||||
// GPP_C14 missing
|
||||
// GPP_C15 missing
|
||||
// GPP_C16 missing
|
||||
// GPP_C17 missing
|
||||
// GPP_C18 missing
|
||||
// GPP_C19 missing
|
||||
// GPP_C20 missing
|
||||
// GPP_C21 missing
|
||||
// GPP_C22 missing
|
||||
// GPP_C23 missing
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_CFG_GPO(GPP_D4, 1, DEEP), // GPIO_LAN_EN
|
||||
// GPP_D5 (SSD2_CLKREQ#) configured by FSP
|
||||
PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
|
||||
// GPP_D7 (WLAN_CLKREQ#) configured by FSP
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
|
||||
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN
|
||||
PAD_CFG_GPO(GPP_D15, 1, DEEP), // GPP_D2_SDCARD_RST#
|
||||
PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_CFG_GPI(GPP_D19, NONE, DEEP), // SATA_LED#
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // GPP_E3_WLAN_EN
|
||||
// GPP_E4 missing
|
||||
// GPP_E5 missing
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
PAD_CFG_GPO(GPP_E7, 0, DEEP), // SMI#
|
||||
PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
|
||||
// GPP_E9 missing
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
PAD_CFG_GPI(GPP_E16, NONE, DEEP), // SDCARD_WAKE#
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
// GPP_E18 (TBT_LSX0_TXD) configured by FSP
|
||||
// GPP_E19 (TBT_LSX0_RXD) configured by FSP
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
|
||||
// GPP_F5 (CNVI_CLKREQ) configured by FSP
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
// GPP_F8 missing
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE), // BOARD_ID3
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE), // BOARD_ID1
|
||||
PAD_NC(GPP_F15, NONE), // BOARD_ID2
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN
|
||||
PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
|
||||
// GPP_F19 (GLAN_CLKREQ6#) configured by FSP
|
||||
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
|
||||
// GPP_H10 (UART0_RX) configured in bootblock
|
||||
// GPP_H11 (UART0_TX) configured in bootblock
|
||||
_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000), // SATA1_DEVSLP1
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
// GPP_H14 missing
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
|
||||
// GPP_H16 missing
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
|
||||
// GPP_H19 (SSD1_CLKREQ#) configured by FSP
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PM_CLKRUN#
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
// GPP_H23 (CARD_CLKREQ#) configured by FSP
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_T ------- */
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x155851b1, /* Subsystem ID */
|
||||
19, /* Number of entries */
|
||||
0x0205001a, 0x02048003, 0x0205001a, 0x0204c003,
|
||||
AZALIA_SUBVENDOR(0, 0x155851b1),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
0x02050038, 0x02047901, 0x02050007, 0x02040202,
|
||||
0x02050008, 0x02046a0e, 0x0205001b, 0x02040a4b,
|
||||
0x0205003c, 0x02040354, 0x0205003c, 0x02040314,
|
||||
0x02050046, 0x02040004, 0x05750003, 0x057409a2,
|
||||
0x02050010, 0x02040020, 0x02050036, 0x02043050,
|
||||
0x00170503, 0x0143b000, 0x0213b000, 0x02170740,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
chip soc/intel/alderlake
|
||||
register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
|
||||
.tdp_pl1_override = 20,
|
||||
.tdp_pl2_override = 56,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x51b1 inherit
|
||||
|
||||
device ref pcie4_0 on
|
||||
# CPU RP#1 x4, Clock 0 (SSD2)
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_src = 0,
|
||||
.clk_req = 0,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie4_1 on
|
||||
# CPU RP#3 x4, Clock 4 (SSD1)
|
||||
register "cpu_pcie_rp[CPU_RP(3)]" = "{
|
||||
.clk_src = 4,
|
||||
.clk_req = 4,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref tbt_pcie_rp0 on end
|
||||
device ref tcss_xhci on
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
end
|
||||
device ref tcss_dma0 on end
|
||||
device ref xhci on
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 (USB-C)
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 (Thunderbolt)
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
|
||||
end
|
||||
device ref i2c0 on
|
||||
# Touchpad I2C bus
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN0412""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""FTCS1000""
|
||||
register "generic.desc" = ""FocalTech Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 38 on end
|
||||
end
|
||||
end
|
||||
device ref sata off end
|
||||
device ref pcie_rp5 on
|
||||
# PCIe RP#5 x1, Clock 2 (WLAN)
|
||||
register "pch_pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# PCIe RP#6 x1, Clock 5 (CARD)
|
||||
register "pch_pcie_rp[PCH_RP(6)]" = "{
|
||||
.clk_src = 5,
|
||||
.clk_req = 5,
|
||||
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
# PCIe RP#8 x1, Clock 6 (GLAN)
|
||||
register "pch_pcie_rp[PCH_RP(8)]" = "{
|
||||
.clk_src = 6,
|
||||
.clk_req = 6,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR5,
|
||||
.ect = true,
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
};
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||
mupd->FspmConfig.GpioOverride = 0;
|
||||
|
||||
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
Loading…
Reference in New Issue