From 6876f49b7e3e8e750dc40ddbe1c37b6ab12c0153 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 30 May 2022 14:18:32 +0530 Subject: [PATCH] soc/intel/meteorlake: Refactor bootblock SoC programming code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch ensures the IP initialization being done as part of MTL bootblock code is able to complete the bootblock phase without any visible hang. The re-ordering in the MTL bootblock SoC programming is required to ensure the SA early initialization is taking place prior to performing any PCI Read/Write operation (like P2SB bar enabling for IOE die etc.). Additionally, Fast SPI init takes place prior to enabling ROM caching etc. BUG=b:224325352 TEST= Able to build and start booting the MTL simics. Without this change, the code execution is stuck as below: [NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8) [DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz [DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018 [DEBUG]  CPU: AES supported, TXT supported, VT supported [DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P [DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC [DEBUG]  IGD: device id ffff (rev ff) is Unknown [INFO ]  PMC: Using default GPE route. [INFO ]  VBNV: CMOS invalid, restoring from flash [ERROR]  init_vbnv: failed to locate NVRAM [EMERG]  Cannot locate primary CBFS Able to detect the Flash and reading the SPI flash layout in proper with this change as below: [NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8) [DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz [DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018 [DEBUG]  CPU: AES supported, TXT supported, VT supported [DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P [DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG]  IGD: device id ffff (rev ff) is Unknown [INFO ]  PMC: Using default GPE route. [INFO ]  VBNV: CMOS invalid, restoring from flash [DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1804000. [DEBUG]  FMAP: base = 0x0 size = 0x2000000 #areas = 33 [DEBUG]  FMAP: area RW_NVRAM found @ 112b000 (24576 bytes) [INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Signed-off-by: Subrata Banik Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793 Tested-by: build bot (Jenkins) Reviewed-by: Tarun Tuli --- .../intel/meteorlake/bootblock/bootblock.c | 2 +- src/soc/intel/meteorlake/bootblock/soc_die.c | 34 +++++++++++-------- 2 files changed, 20 insertions(+), 16 deletions(-) diff --git a/src/soc/intel/meteorlake/bootblock/bootblock.c b/src/soc/intel/meteorlake/bootblock/bootblock.c index 74e9dca663..c7e1826d23 100644 --- a/src/soc/intel/meteorlake/bootblock/bootblock.c +++ b/src/soc/intel/meteorlake/bootblock/bootblock.c @@ -11,8 +11,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { - bootblock_ioe_die_early_init(); bootblock_soc_die_early_init(); + bootblock_ioe_die_early_init(); } void bootblock_soc_init(void) diff --git a/src/soc/intel/meteorlake/bootblock/soc_die.c b/src/soc/intel/meteorlake/bootblock/soc_die.c index b852e10a91..f48981c07c 100644 --- a/src/soc/intel/meteorlake/bootblock/soc_die.c +++ b/src/soc/intel/meteorlake/bootblock/soc_die.c @@ -69,22 +69,8 @@ static void soc_die_early_iorange_init(void) pch_enable_lpc(); } -void bootblock_soc_die_early_init(void) +static void soc_die_early_ip_init(void) { - const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { - { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, - }; - - bootblock_systemagent_early_init(); - - /* Enable MCHBAR early, needed by IOC driver */ - sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); - - fast_spi_cache_bios_region(); - soc_die_early_iorange_init(); - if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) - uart_bootblock_init(); - /* * Perform P2SB configuration before any another controller initialization as the * controller might want to perform PCR settings. @@ -102,6 +88,24 @@ void bootblock_soc_die_early_init(void) soc_die_config_pwrmbase(); } +void bootblock_soc_die_early_init(void) +{ + const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + }; + + bootblock_systemagent_early_init(); + soc_die_early_ip_init(); + + /* Enable MCHBAR early, needed by IOC driver */ + sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); + + fast_spi_cache_bios_region(); + soc_die_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + static void soc_die_config_acpibase(void) { uint32_t pmc_reg_value;