sb/intel/i82801{g,j}x: Remove unused smi.c files
Now that all targets featuring these southbridges use SMM_TSEG these files are unused. Change-Id: Ic3a1d790f3595e98a8d33e6e8274cb72ad356a89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30018 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
97ca02cb17
commit
6880a7a18b
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@ -1,185 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <string.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801gx.h"
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/* I945 */
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#define SMRAM 0x9d
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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static u16 pmbase = DEFAULT_PMBASE;
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extern uint8_t smm_relocation_start, smm_relocation_end;
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static void *default_smm_area = NULL;
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static void smm_relocate(void)
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{
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u32 smi_en;
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u16 pm1_en;
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printk(BIOS_DEBUG, "Initializing SMM handler...");
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pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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smi_en = inl(pmbase + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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default_smm_area = backup_default_smm_area();
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/* copy the SMM relocation code */
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memcpy((void *)0x38000, &smm_relocation_start,
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&smm_relocation_end - &smm_relocation_start);
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wbinvd();
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printk(BIOS_DEBUG, "\n");
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dump_smi_status(reset_smi_status());
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dump_pm1_status(reset_pm1_status());
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dump_gpe0_status(reset_gpe0_status());
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dump_alt_gp_smi_status(reset_alt_gp_smi_status());
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dump_tco_status(reset_tco_status());
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/* Enable SMI generation:
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* - on TCO events
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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*/
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smi_en = 0; /* reset SMI enables */
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#if 0
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smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
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#endif
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smi_en |= TCO_EN;
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smi_en |= APMC_EN;
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
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* periodic SMIs.
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*/
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smi_en |= PERIODIC_EN;
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#endif
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smi_en |= SLP_SMI_EN;
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smi_en |= BIOS_EN;
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/* The following need to be on for SMIs to happen */
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smi_en |= EOS | GBL_SMI_EN;
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outl(smi_en, pmbase + SMI_EN);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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outw(pm1_en, pmbase + PM1_EN);
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/**
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* There are several methods of raising a controlled SMI# via
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* software, among them:
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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* I'm not too worried about the better of the methods at the moment
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*/
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/* raise an SMI interrupt */
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printk(BIOS_SPEW, " ... raise SMI#\n");
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outb(0x00, 0xb2);
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}
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static int smm_handler_copied = 0;
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static void smm_install(void)
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{
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/* The first CPU running this gets to copy the SMM handler. But not all
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* of them.
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*/
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if (smm_handler_copied)
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return;
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smm_handler_copied = 1;
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/* if we're resuming from S3, the SMM code is already in place,
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* so don't copy it again to keep the current SMM state */
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if (!acpi_is_wakeup_s3()) {
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/* enable the SMM memory window */
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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D_OPEN | G_SMRAME | C_BASE_SEG);
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/* copy the real SMM handler */
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memcpy((void *)0xa0000, _binary_smm_start,
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_binary_smm_end - _binary_smm_start);
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wbinvd();
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}
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/* close the SMM memory window and enable normal SMM */
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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G_SMRAME | C_BASE_SEG);
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}
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void smm_init(void)
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{
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/* Put SMM code to 0xa0000 */
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smm_install();
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/* Put relocation code to 0x38000 and relocate SMBASE */
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smm_relocate();
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/* We're done. Make sure SMIs can happen! */
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smi_set_eos();
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}
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void smm_init_completion(void)
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{
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restore_default_smm_area(default_smm_area);
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}
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void smm_lock(void)
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{
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/* LOCK the SMM memory window and enable normal SMM.
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* After running this function, only a full reset can
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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D_LCK | G_SMRAME | C_BASE_SEG);
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}
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@ -1,181 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <string.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801jx.h"
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/* I945/GM45 */
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#define SMRAM 0x9d
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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static u16 pmbase = DEFAULT_PMBASE;
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extern uint8_t smm_relocation_start, smm_relocation_end;
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static void *default_smm_area = NULL;
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static void smm_relocate(void)
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{
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u32 smi_en;
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u16 pm1_en;
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printk(BIOS_DEBUG, "Initializing SMM handler...");
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pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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smi_en = inl(pmbase + SMI_EN);
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if (smi_en & GBL_SMI_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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default_smm_area = backup_default_smm_area();
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/* copy the SMM relocation code */
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memcpy((void *)0x38000, &smm_relocation_start,
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&smm_relocation_end - &smm_relocation_start);
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wbinvd();
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printk(BIOS_DEBUG, "\n");
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dump_smi_status(reset_smi_status());
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dump_pm1_status(reset_pm1_status());
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dump_gpe0_status(reset_gpe0_status());
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dump_alt_gp_smi_status(reset_alt_gp_smi_status());
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dump_tco_status(reset_tco_status());
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/* Enable SMI generation:
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* - on TCO events
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* - on APMC writes (io 0xb2)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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*/
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smi_en = 0; /* reset SMI enables */
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smi_en |= TCO_EN;
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smi_en |= APMC_EN;
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in i82801jx.h to debug using
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* periodic SMIs.
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*/
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smi_en |= PERIODIC_EN;
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#endif
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smi_en |= BIOS_EN;
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/* The following need to be on for SMIs to happen */
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smi_en |= EOS | GBL_SMI_EN;
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outl(smi_en, pmbase + SMI_EN);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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outw(pm1_en, pmbase + PM1_EN);
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/**
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* There are several methods of raising a controlled SMI# via
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* software, among them:
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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* I'm not too worried about the better of the methods at the moment
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*/
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/* raise an SMI interrupt */
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printk(BIOS_SPEW, " ... raise SMI#\n");
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outb(0x00, 0xb2);
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}
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static int smm_handler_copied = 0;
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static void smm_install(void)
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{
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/* The first CPU running this gets to copy the SMM handler. But not all
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* of them.
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*/
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if (smm_handler_copied)
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return;
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smm_handler_copied = 1;
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/* if we're resuming from S3, the SMM code is already in place,
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* so don't copy it again to keep the current SMM state */
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if (!acpi_is_wakeup_s3()) {
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/* enable the SMM memory window */
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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D_OPEN | G_SMRAME | C_BASE_SEG);
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/* copy the real SMM handler */
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memcpy((void *)0xa0000, _binary_smm_start,
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_binary_smm_end - _binary_smm_start);
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wbinvd();
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}
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/* close the SMM memory window and enable normal SMM */
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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G_SMRAME | C_BASE_SEG);
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}
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void smm_init(void)
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{
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/* Put SMM code to 0xa0000 */
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smm_install();
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/* Put relocation code to 0x38000 and relocate SMBASE */
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smm_relocate();
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/* We're done. Make sure SMIs can happen! */
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smi_set_eos();
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}
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void smm_init_completion(void)
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{
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restore_default_smm_area(default_smm_area);
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}
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void smm_lock(void)
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{
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/* LOCK the SMM memory window and enable normal SMM.
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* After running this function, only a full reset can
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
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D_LCK | G_SMRAME | C_BASE_SEG);
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}
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