From 688257409330b9d12455c6997b0f57f128cd207b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Tue, 27 Oct 2015 14:31:18 +0200
Subject: [PATCH] asrock/e350m1: Add ACPI S3 support
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To store memory configuration in SPI flash currently adds
some 150 ms delay in ramstage, visible in timestamps listing
at 75:cbmem post.

Change-Id: I1160259054b58e9a8df2a105c730e0f4140be1f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12215
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/mainboard/asrock/e350m1/Kconfig     |  1 +
 src/mainboard/asrock/e350m1/buildOpts.c |  4 ++--
 src/mainboard/asrock/e350m1/romstage.c  | 26 ++++++++++++++++++++-----
 3 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index fa93d13464..1c53212124 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
+	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_4096
 	select GFXUMA
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 041e1ddf08..140ece4338 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -115,7 +115,7 @@
 #define AGESA_ENTRY_INIT_LATE                     TRUE
 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 #define AGESA_ENTRY_INIT_RESUME                   TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
+#define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
 /*
@@ -187,7 +187,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 //#define BLDCFG_USE_HT_ASSIST                    TRUE
 //#define BLDCFG_USE_ATM_MODE                     TRUE
 //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE       Nfcm
-#define BLDCFG_S3_LATE_RESTORE                    FALSE
+#define BLDCFG_S3_LATE_RESTORE                    TRUE
 //#define BLDCFG_USE_32_BYTE_REFRESH              FALSE
 //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY   FALSE
 //#define BLDCFG_PLATFORM_POWER_POLICY_MODE       Performance
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index bf383950bd..50f3f6b56a 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -17,6 +17,7 @@
 #include <string.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
@@ -33,6 +34,7 @@
 #include <cpu/x86/lapic.h>
 #include <sb_cimx.h>
 #include "SBPLATFORM.h"
+#include <cpu/amd/agesa/s3_resume.h>
 
 
 #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
@@ -77,12 +79,26 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x39);
 	agesawrapper_amdinitearly();
 
-	post_code(0x40);
-	agesawrapper_amdinitpost();
+	int s3resume = acpi_is_wakeup_s3();
+	if (!s3resume) {
+		post_code(0x40);
+		agesawrapper_amdinitpost();
 
-	post_code(0x41);
-	agesawrapper_amdinitenv();
-	amd_initenv();
+		post_code(0x42);
+		agesawrapper_amdinitenv();
+		amd_initenv();
+
+	} else { 			/* S3 detect */
+		printk(BIOS_INFO, "S3 detected\n");
+
+		post_code(0x60);
+		agesawrapper_amdinitresume();
+
+		agesawrapper_amds3laterestore();
+
+		post_code(0x61);
+		prepare_for_resume();
+	}
 
 	post_code(0x50);
 	copy_and_run();