From 688f09f97ad5b25e3374653eebafbb5220032feb Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 7 Dec 2021 00:38:29 +0100 Subject: [PATCH] soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100 Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=None Signed-off-by: Felix Held Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59933 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/stoneyridge/southbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index de27ac540a..63bfd832b3 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -242,7 +242,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - spi_write16(SPI100_ENABLE, SPI_USE_SPI100); + spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE)); } static void sb_disable_4dw_burst(void)