fsp_rangeley: Switch to per-device ACPI

Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7046
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

src/cpu/intel/fsp_model_406dx/acpi.c

@@ -50,47 +50,44 @@ static int get_cores_per_package(void)
 	return cores;
 }
 
-static int generate_C_state_entries(void)
+static void generate_C_state_entries(void)
 {
 	struct cpu_info *info;
 	struct cpu_driver *cpu;
-	int len, lenif;
 	struct device *lapic;
 	struct cpu_intel_model_406dx_config *conf = NULL;
 
 	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
 	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
 	if (!lapic)
-		return 0;
+		return;
 	conf = lapic->chip_info;
 	if (!conf)
-		return 0;
+		return;
 
 	/* Find CPU map of supported C-states */
 	info = cpu_info();
 	if (!info)
-		return 0;
+		return;
 	cpu = find_cpu_driver(info->cpu);
 	if (!cpu || !cpu->cstates)
-		return 0;
+		return;
 
-	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	acpigen_emit_byte(0x14);		/* MethodOp */
-	len += acpigen_write_len_f();		/* PkgLength */
+	acpigen_write_len_f();		/* PkgLength */
-	len += acpigen_emit_namestring("_CST");
+	acpigen_emit_namestring("_CST");
-	len += acpigen_emit_byte(0x00);		/* No Arguments */
+	acpigen_emit_byte(0x00);		/* No Arguments */
 
 	/* If running on AC power */
-	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	acpigen_emit_byte(0xa0);		/* IfOp */
-	lenif = acpigen_write_len_f();		/* PkgLength */
+	acpigen_write_len_f();		/* PkgLength */
-	lenif += acpigen_emit_namestring("PWRS");
+	acpigen_emit_namestring("PWRS");
-	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	acpigen_emit_byte(0xa4);	/* ReturnOp */
-	acpigen_patch_len(lenif - 1);
+	acpigen_pop_len();
-	len += lenif;
 
 	/* Else on battery power */
-	len += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	acpigen_emit_byte(0xa4);	/* ReturnOp */
-	acpigen_patch_len(len - 1);
+	acpigen_pop_len();
-	return len;
 }
 
 static acpi_tstate_t tss_table_fine[] = {
@@ -122,31 +119,27 @@ static acpi_tstate_t tss_table_coarse[] = {
 	{ 13, 125, 0, 0x19, 0 },
 };
 
-static int generate_T_state_entries(int core, int cores_per_package)
+static void generate_T_state_entries(int core, int cores_per_package)
 {
-	int len;
-
 	/* Indicate SW_ALL coordination for T-states */
-	len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+	acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
 
 	/* Indicate FFixedHW so OS will use MSR */
-	len += acpigen_write_empty_PTC();
+	acpigen_write_empty_PTC();
 
 	/* Set a T-state limit that can be modified in NVS */
-	len += acpigen_write_TPC("\\TLVL");
+	acpigen_write_TPC("\\TLVL");
 
 	/*
 	 * CPUID.(EAX=6):EAX[5] indicates support
 	 * for extended throttle levels.
 	 */
 	if (cpuid_eax(6) & (1 << 5))
-		len += acpigen_write_TSS_package(
+		acpigen_write_TSS_package(
 			ARRAY_SIZE(tss_table_fine), tss_table_fine);
 	else
-		len += acpigen_write_TSS_package(
+		acpigen_write_TSS_package(
 			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
-
-	return len;
 }
 
 static int calculate_power(int tdp, int p1_ratio, int ratio)
@@ -170,9 +163,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
 	return (int)power;
 }
 
-static int generate_P_state_entries(int core, int cores_per_package)
+static void generate_P_state_entries(int core, int cores_per_package)
 {
-	int len, len_pss;
 	int ratio_min, ratio_max, ratio_turbo, ratio_step;
 	int coord_type, power_max, num_entries;
 	int ratio, power, clock, clock_max;
@@ -202,16 +194,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
 
 
 	/* Write _PCT indicating use of FFixedHW */
-	len = acpigen_write_empty_PCT();
+	acpigen_write_empty_PCT();
 
 	/* Write _PPC with no limit on supported P-state */
-	len += acpigen_write_PPC_NVS();
+	acpigen_write_PPC_NVS();
 
 	/* Write PSD indicating configured coordination type */
-	len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
+	acpigen_write_PSD_package(core, cores_per_package, coord_type);
 
 	/* Add P-state entries in _PSS table */
-	len += acpigen_write_name("_PSS");
+	acpigen_write_name("_PSS");
 
 	/* Determine ratio points */
 	ratio_step = PSS_RATIO_STEP;
@@ -224,13 +216,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
 	/* P[T] is Turbo state if enabled */
 	if (get_turbo_state() == TURBO_ENABLED) {
 		/* _PSS package count including Turbo */
-		len_pss = acpigen_write_package(num_entries + 2);
+		acpigen_write_package(num_entries + 2);
 
 		msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
 		ratio_turbo = msr.lo & 0xff;
 
 		/* Add entry for Turbo ratio */
-		len_pss += acpigen_write_PSS_package(
+		acpigen_write_PSS_package(
 			clock_max + 1,		/*MHz*/
 			power_max,		/*mW*/
 			PSS_LATENCY_TRANSITION,	/*lat1*/
@@ -239,11 +231,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
 			ratio_turbo << 8);	/*status*/
 	} else {
 		/* _PSS package count without Turbo */
-		len_pss = acpigen_write_package(num_entries + 1);
+		acpigen_write_package(num_entries + 1);
 	}
 
 	/* First regular entry is max non-turbo ratio */
-	len_pss += acpigen_write_PSS_package(
+	acpigen_write_PSS_package(
 		clock_max,		/*MHz*/
 		power_max,		/*mW*/
 		PSS_LATENCY_TRANSITION,	/*lat1*/
@@ -259,7 +251,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
 		power = calculate_power(power_max, ratio_max, ratio);
 		clock = ratio * RANGELEY_BCLK;
 
-		len_pss += acpigen_write_PSS_package(
+		acpigen_write_PSS_package(
 			clock,			/*MHz*/
 			power,			/*mW*/
 			PSS_LATENCY_TRANSITION,	/*lat1*/
@@ -269,15 +261,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
 	}
 
 	/* Fix package length */
-	len_pss--;
+	acpigen_pop_len();
-	acpigen_patch_len(len_pss);
-
-	return len + len_pss;
 }
 
 void generate_cpu_entries(void)
 {
-	int len_pr;
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 	int totalcores = dev_count_cpu();
 	int cores_per_package = get_cores_per_package();
@@ -294,23 +282,22 @@ void generate_cpu_entries(void)
 			}
 
 			/* Generate processor \_PR.CPUx */
-			len_pr = acpigen_write_processor(
+			acpigen_write_processor(
 				(cpuID-1)*cores_per_package+coreID-1,
 				pcontrol_blk, plen);
 
 			/* Generate P-state tables */
-			len_pr += generate_P_state_entries(
+			generate_P_state_entries(
 				cpuID-1, cores_per_package);
 
 			/* Generate C-state tables */
-			len_pr += generate_C_state_entries();
+			generate_C_state_entries();
 
 			/* Generate T-state tables */
-			len_pr += generate_T_state_entries(
+			generate_T_state_entries(
 				cpuID-1, cores_per_package);
 
-			len_pr--;
+			acpigen_pop_len();
-			acpigen_patch_len(len_pr);
 		}
 	}
 }

src/mainboard/intel/mohonpeak/acpi_tables.c

@@ -33,14 +33,9 @@
 #include <southbridge/intel/fsp_rangeley/nvs.h>
 #include <northbridge/intel/fsp_rangeley/northbridge.h>
 
-extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
-
 static global_nvs_t *gnvs_;
 
-static void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	gnvs_ = gnvs;
 	memset((void *)gnvs, 0, sizeof(*gnvs));
@@ -89,173 +84,3 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 	return current;
 }
-
-unsigned long acpi_fill_ssdt_generator(unsigned long current,
-					const char *oem_table_id)
-{
-	u32 lens, bmbound;
-	char pscope[] = "\\_SB.PCI0";
-
-	bmbound = sideband_read(B_UNIT, BMBOUND);
-	lens = acpigen_write_scope(pscope);
-	lens += acpigen_write_name_dword("BMBD", bmbound);
-	generate_cpu_entries();
-	acpigen_patch_len(lens - 1);
-	return (unsigned long) (acpigen_get_current());
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
-	// Not implemented
-	return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
-	/* No NUMA, no SRAT */
-	return current;
-}
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
-
-#define ALIGN_CURRENT current = (ALIGN(current, 16))
-unsigned long write_acpi_tables(unsigned long start)
-{
-	unsigned long current;
-	int i;
-	acpi_rsdp_t *rsdp;
-	acpi_rsdt_t *rsdt;
-	acpi_xsdt_t *xsdt;
-	acpi_hpet_t *hpet;
-	acpi_madt_t *madt;
-	acpi_mcfg_t *mcfg;
-	acpi_fadt_t *fadt;
-	acpi_facs_t *facs;
-#if CONFIG_HAVE_ACPI_SLIC
-	acpi_header_t *slic;
-#endif
-	acpi_header_t *ssdt;
-	acpi_header_t *dsdt;
-
-	current = start;
-
-	/* Align ACPI tables to 16byte */
-	ALIGN_CURRENT;
-
-	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
-
-	/* We need at least an RSDP and an RSDT Table */
-	rsdp = (acpi_rsdp_t *) current;
-	current += sizeof(acpi_rsdp_t);
-	ALIGN_CURRENT;
-	rsdt = (acpi_rsdt_t *) current;
-	current += sizeof(acpi_rsdt_t);
-	ALIGN_CURRENT;
-	xsdt = (acpi_xsdt_t *) current;
-	current += sizeof(acpi_xsdt_t);
-	ALIGN_CURRENT;
-
-	/* clear all table memory */
-	memset((void *) start, 0, current - start);
-
-	acpi_write_rsdp(rsdp, rsdt, xsdt);
-	acpi_write_rsdt(rsdt);
-	acpi_write_xsdt(xsdt);
-
-	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
-	facs = (acpi_facs_t *) current;
-	current += sizeof(acpi_facs_t);
-	ALIGN_CURRENT;
-	acpi_create_facs(facs);
-
-	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
-	dsdt = (acpi_header_t *) current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-
-	ALIGN_CURRENT;
-
-	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
-	fadt = (acpi_fadt_t *) current;
-	current += sizeof(acpi_fadt_t);
-	ALIGN_CURRENT;
-
-	acpi_create_fadt(fadt, facs, dsdt);
-	acpi_add_table(rsdp, fadt);
-
-	/*
-	 * We explicitly add these tables later on:
-	 */
-	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
-
-	hpet = (acpi_hpet_t *) current;
-	current += sizeof(acpi_hpet_t);
-	ALIGN_CURRENT;
-	acpi_create_hpet(hpet);
-	acpi_add_table(rsdp, hpet);
-
-	/* If we want to use HPET Timers Linux wants an MADT */
-	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
-
-	madt = (acpi_madt_t *) current;
-	acpi_create_madt(madt);
-	current += madt->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, madt);
-
-	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
-	mcfg = (acpi_mcfg_t *) current;
-	acpi_create_mcfg(mcfg);
-	current += mcfg->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, mcfg);
-
-	/* Pack GNVS into the ACPI table area */
-	for (i=0; i < dsdt->length; i++) {
-		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
-			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
-			     "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
-			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
-			acpi_save_gnvs(current);
-			break;
-		}
-	}
-
-	/* And fill it */
-	acpi_create_gnvs((global_nvs_t *)current);
-
-	/* And tell SMI about it */
-#if CONFIG_HAVE_SMI_HANDLER
-	smm_setup_structures((void *)current, NULL, NULL);
-#endif
-
-	current += sizeof(global_nvs_t);
-	ALIGN_CURRENT;
-
-	/* We patched up the DSDT, so we need to recalculate the checksum */
-	dsdt->checksum = 0;
-	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
-
-	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
-		     dsdt->length);
-
-#if CONFIG_HAVE_ACPI_SLIC
-	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
-	slic = (acpi_header_t *)current;
-	current += acpi_create_slic(current);
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, slic);
-#endif
-
-	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
-	current += ssdt->length;
-	acpi_add_table(rsdp, ssdt);
-	ALIGN_CURRENT;
-
-	printk(BIOS_DEBUG, "current = %lx\n", current);
-	printk(BIOS_INFO, "ACPI: done.\n");
-	return current;
-}

src/northbridge/intel/fsp_rangeley/Kconfig

@@ -21,6 +21,7 @@
 config NORTHBRIDGE_INTEL_FSP_RANGELEY
 	bool
 	select CPU_INTEL_FSP_MODEL_406DX
+	select PER_DEVICE_ACPI_TABLES
 
 if NORTHBRIDGE_INTEL_FSP_RANGELEY
 

src/northbridge/intel/fsp_rangeley/acpi.c

@@ -30,6 +30,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <build.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include "northbridge.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)
@@ -64,3 +66,15 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 	return current;
 }
+
+void northbridge_acpi_fill_ssdt_generator(void)
+{
+	u32 bmbound;
+	char pscope[] = "\\_SB.PCI0";
+
+	bmbound = sideband_read(B_UNIT, BMBOUND);
+	acpigen_write_scope(pscope);
+	acpigen_write_name_dword("BMBD", bmbound);
+	acpigen_pop_len();
+	generate_cpu_entries();
+}

src/northbridge/intel/fsp_rangeley/northbridge.c

@@ -212,6 +212,18 @@ static void northbridge_enable(device_t dev)
 {
 }
 
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
 static struct pci_operations intel_pci_ops = {
 	.set_subsystem    = intel_set_subsystem,
 };
@@ -231,6 +243,7 @@ static struct device_operations mc_ops = {
 	.set_resources    = mc_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = northbridge_init,
+	.acpi_fill_ssdt_generator = northbridge_acpi_fill_ssdt_generator,
 	.enable           = northbridge_enable,
 	.scan_bus         = 0,
 	.ops_pci          = &intel_pci_ops,

src/northbridge/intel/fsp_rangeley/northbridge.h

@@ -72,6 +72,7 @@ void dump_pci_devices(void);
 void dump_spd_registers(void);
 void dump_mem(unsigned start, unsigned end);
 void report_platform_info(void);
+void northbridge_acpi_fill_ssdt_generator(void);
 
 #endif /* #ifndef __ASSEMBLER__ */
 #endif /* #ifndef __ACPI__ */

src/southbridge/intel/fsp_rangeley/acpi/globalnvs.asl

@@ -32,7 +32,8 @@ Name(\DSEN, 1)		// Display Output Switching Enable
  */
 
 
-OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00)
+External(NVSA)
+OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */

src/southbridge/intel/fsp_rangeley/lpc.c

@@ -31,8 +31,13 @@
 #include <arch/acpi.h>
 #include <cpu/cpu.h>
 #include <elog.h>
+#include <string.h>
+#include <cbmem.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include "soc.h"
 #include "irq.h"
+#include "nvs.h"
 
 #define NMI_OFF	0
 
@@ -426,6 +431,26 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
+static void southbridge_inject_dsdt(void)
+{
+	global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+
+	if (gnvs) {
+		memset(gnvs, 0, sizeof(*gnvs));
+		acpi_create_gnvs(gnvs);
+		acpi_save_gnvs((unsigned long)gnvs);
+#if CONFIG_HAVE_SMI_HANDLER
+		/* And tell SMI about it */
+		smm_setup_structures(gnvs, NULL, NULL);
+#endif
+
+		/* Add it to DSDT.  */
+		acpigen_write_scope("\\");
+		acpigen_write_name_dword("NVSA", (u32) gnvs);
+		acpigen_pop_len();
+	}
+}
+
 static struct pci_operations pci_ops = {
 	.set_subsystem = set_subsystem,
 };
@@ -435,6 +460,8 @@ static struct device_operations device_ops = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= soc_lpc_enable_resources,
 	.init			= lpc_init,
+	.write_acpi_tables      = acpi_write_hpet,
+	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
 	.enable			= soc_lpc_enable,
 	.scan_bus		= scan_static_bus,
 	.ops_pci		= &pci_ops,

src/southbridge/intel/fsp_rangeley/nvs.h

@@ -149,6 +149,7 @@ typedef struct {
 
 } __attribute__((packed)) global_nvs_t;
 
+void acpi_create_gnvs(global_nvs_t *gnvs);
 #ifdef __SMM__
 /* Used in SMM to find the ACPI GNVS address */
 global_nvs_t *smm_get_gnvs(void);