fsp_rangeley: Switch to per-device ACPI
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7046 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
This commit is contained in:
Vladimir Serbinenko
parent
67bfbfdfeb
commit
689ddf6832
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@ -50,47 +50,44 @@ static int get_cores_per_package(void)
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return cores;
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}
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static int generate_C_state_entries(void)
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static void generate_C_state_entries(void)
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{
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struct cpu_info *info;
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struct cpu_driver *cpu;
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int len, lenif;
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struct device *lapic;
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struct cpu_intel_model_406dx_config *conf = NULL;
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/* Find the SpeedStep CPU in the device tree using magic APIC ID */
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lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
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if (!lapic)
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return 0;
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return;
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conf = lapic->chip_info;
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if (!conf)
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return 0;
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return;
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/* Find CPU map of supported C-states */
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info = cpu_info();
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if (!info)
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return 0;
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return;
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cpu = find_cpu_driver(info->cpu);
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if (!cpu || !cpu->cstates)
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return 0;
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return;
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len = acpigen_emit_byte(0x14); /* MethodOp */
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len += acpigen_write_len_f(); /* PkgLength */
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len += acpigen_emit_namestring("_CST");
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len += acpigen_emit_byte(0x00); /* No Arguments */
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acpigen_emit_byte(0x14); /* MethodOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("_CST");
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acpigen_emit_byte(0x00); /* No Arguments */
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/* If running on AC power */
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len += acpigen_emit_byte(0xa0); /* IfOp */
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lenif = acpigen_write_len_f(); /* PkgLength */
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lenif += acpigen_emit_namestring("PWRS");
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lenif += acpigen_emit_byte(0xa4); /* ReturnOp */
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acpigen_patch_len(lenif - 1);
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len += lenif;
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acpigen_emit_byte(0xa0); /* IfOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("PWRS");
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acpigen_emit_byte(0xa4); /* ReturnOp */
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acpigen_pop_len();
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/* Else on battery power */
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len += acpigen_emit_byte(0xa4); /* ReturnOp */
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acpigen_patch_len(len - 1);
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return len;
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acpigen_emit_byte(0xa4); /* ReturnOp */
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acpigen_pop_len();
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}
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static acpi_tstate_t tss_table_fine[] = {
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@ -122,31 +119,27 @@ static acpi_tstate_t tss_table_coarse[] = {
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{ 13, 125, 0, 0x19, 0 },
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};
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static int generate_T_state_entries(int core, int cores_per_package)
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static void generate_T_state_entries(int core, int cores_per_package)
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{
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int len;
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/* Indicate SW_ALL coordination for T-states */
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len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
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acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
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/* Indicate FFixedHW so OS will use MSR */
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len += acpigen_write_empty_PTC();
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acpigen_write_empty_PTC();
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/* Set a T-state limit that can be modified in NVS */
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len += acpigen_write_TPC("\\TLVL");
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acpigen_write_TPC("\\TLVL");
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/*
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* CPUID.(EAX=6):EAX[5] indicates support
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* for extended throttle levels.
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*/
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if (cpuid_eax(6) & (1 << 5))
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len += acpigen_write_TSS_package(
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acpigen_write_TSS_package(
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ARRAY_SIZE(tss_table_fine), tss_table_fine);
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else
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len += acpigen_write_TSS_package(
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acpigen_write_TSS_package(
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ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
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return len;
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}
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static int calculate_power(int tdp, int p1_ratio, int ratio)
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@ -170,9 +163,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
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return (int)power;
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}
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static int generate_P_state_entries(int core, int cores_per_package)
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static void generate_P_state_entries(int core, int cores_per_package)
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{
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int len, len_pss;
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int ratio_min, ratio_max, ratio_turbo, ratio_step;
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int coord_type, power_max, num_entries;
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int ratio, power, clock, clock_max;
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@ -202,16 +194,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
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/* Write _PCT indicating use of FFixedHW */
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len = acpigen_write_empty_PCT();
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acpigen_write_empty_PCT();
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/* Write _PPC with no limit on supported P-state */
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len += acpigen_write_PPC_NVS();
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acpigen_write_PPC_NVS();
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/* Write PSD indicating configured coordination type */
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len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
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acpigen_write_PSD_package(core, cores_per_package, coord_type);
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/* Add P-state entries in _PSS table */
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len += acpigen_write_name("_PSS");
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acpigen_write_name("_PSS");
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/* Determine ratio points */
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ratio_step = PSS_RATIO_STEP;
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@ -224,13 +216,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
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/* P[T] is Turbo state if enabled */
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if (get_turbo_state() == TURBO_ENABLED) {
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/* _PSS package count including Turbo */
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len_pss = acpigen_write_package(num_entries + 2);
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acpigen_write_package(num_entries + 2);
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msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
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ratio_turbo = msr.lo & 0xff;
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/* Add entry for Turbo ratio */
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock_max + 1, /*MHz*/
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power_max, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -239,11 +231,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
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ratio_turbo << 8); /*status*/
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} else {
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/* _PSS package count without Turbo */
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len_pss = acpigen_write_package(num_entries + 1);
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acpigen_write_package(num_entries + 1);
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}
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/* First regular entry is max non-turbo ratio */
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock_max, /*MHz*/
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power_max, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -259,7 +251,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
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power = calculate_power(power_max, ratio_max, ratio);
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clock = ratio * RANGELEY_BCLK;
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock, /*MHz*/
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power, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -269,15 +261,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
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}
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/* Fix package length */
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len_pss--;
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acpigen_patch_len(len_pss);
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return len + len_pss;
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acpigen_pop_len();
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}
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void generate_cpu_entries(void)
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{
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int len_pr;
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int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
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int totalcores = dev_count_cpu();
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int cores_per_package = get_cores_per_package();
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@ -294,23 +282,22 @@ void generate_cpu_entries(void)
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}
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/* Generate processor \_PR.CPUx */
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len_pr = acpigen_write_processor(
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acpigen_write_processor(
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(cpuID-1)*cores_per_package+coreID-1,
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pcontrol_blk, plen);
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/* Generate P-state tables */
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len_pr += generate_P_state_entries(
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generate_P_state_entries(
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cpuID-1, cores_per_package);
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/* Generate C-state tables */
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len_pr += generate_C_state_entries();
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generate_C_state_entries();
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/* Generate T-state tables */
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len_pr += generate_T_state_entries(
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generate_T_state_entries(
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cpuID-1, cores_per_package);
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len_pr--;
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acpigen_patch_len(len_pr);
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acpigen_pop_len();
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}
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}
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}
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@ -33,14 +33,9 @@
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#include <southbridge/intel/fsp_rangeley/nvs.h>
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#include <northbridge/intel/fsp_rangeley/northbridge.h>
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extern const unsigned char AmlCode[];
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#if CONFIG_HAVE_ACPI_SLIC
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unsigned long acpi_create_slic(unsigned long current);
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#endif
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static global_nvs_t *gnvs_;
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static void acpi_create_gnvs(global_nvs_t *gnvs)
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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gnvs_ = gnvs;
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memset((void *)gnvs, 0, sizeof(*gnvs));
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@ -89,173 +84,3 @@ unsigned long acpi_fill_madt(unsigned long current)
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return current;
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}
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unsigned long acpi_fill_ssdt_generator(unsigned long current,
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const char *oem_table_id)
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{
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u32 lens, bmbound;
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char pscope[] = "\\_SB.PCI0";
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bmbound = sideband_read(B_UNIT, BMBOUND);
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lens = acpigen_write_scope(pscope);
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lens += acpigen_write_name_dword("BMBD", bmbound);
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generate_cpu_entries();
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acpigen_patch_len(lens - 1);
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return (unsigned long) (acpigen_get_current());
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}
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unsigned long acpi_fill_slit(unsigned long current)
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{
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// Not implemented
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return current;
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}
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unsigned long acpi_fill_srat(unsigned long current)
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{
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/* No NUMA, no SRAT */
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return current;
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
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#define ALIGN_CURRENT current = (ALIGN(current, 16))
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unsigned long write_acpi_tables(unsigned long start)
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{
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unsigned long current;
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int i;
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acpi_rsdp_t *rsdp;
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acpi_rsdt_t *rsdt;
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acpi_xsdt_t *xsdt;
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acpi_hpet_t *hpet;
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acpi_madt_t *madt;
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acpi_mcfg_t *mcfg;
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acpi_fadt_t *fadt;
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acpi_facs_t *facs;
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#if CONFIG_HAVE_ACPI_SLIC
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acpi_header_t *slic;
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#endif
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acpi_header_t *ssdt;
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acpi_header_t *dsdt;
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current = start;
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/* Align ACPI tables to 16byte */
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ALIGN_CURRENT;
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printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
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/* We need at least an RSDP and an RSDT Table */
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rsdp = (acpi_rsdp_t *) current;
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current += sizeof(acpi_rsdp_t);
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ALIGN_CURRENT;
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rsdt = (acpi_rsdt_t *) current;
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current += sizeof(acpi_rsdt_t);
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ALIGN_CURRENT;
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xsdt = (acpi_xsdt_t *) current;
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current += sizeof(acpi_xsdt_t);
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ALIGN_CURRENT;
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/* clear all table memory */
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memset((void *) start, 0, current - start);
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acpi_write_rsdp(rsdp, rsdt, xsdt);
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acpi_write_rsdt(rsdt);
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acpi_write_xsdt(xsdt);
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printk(BIOS_DEBUG, "ACPI: * FACS\n");
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facs = (acpi_facs_t *) current;
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current += sizeof(acpi_facs_t);
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ALIGN_CURRENT;
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acpi_create_facs(facs);
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printk(BIOS_DEBUG, "ACPI: * DSDT\n");
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dsdt = (acpi_header_t *) current;
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memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
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current += dsdt->length;
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memcpy(dsdt, &AmlCode, dsdt->length);
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ALIGN_CURRENT;
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printk(BIOS_DEBUG, "ACPI: * FADT\n");
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fadt = (acpi_fadt_t *) current;
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current += sizeof(acpi_fadt_t);
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ALIGN_CURRENT;
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acpi_create_fadt(fadt, facs, dsdt);
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acpi_add_table(rsdp, fadt);
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/*
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* We explicitly add these tables later on:
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*/
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printk(BIOS_DEBUG, "ACPI: * HPET\n");
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hpet = (acpi_hpet_t *) current;
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current += sizeof(acpi_hpet_t);
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ALIGN_CURRENT;
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acpi_create_hpet(hpet);
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acpi_add_table(rsdp, hpet);
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/* If we want to use HPET Timers Linux wants an MADT */
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printk(BIOS_DEBUG, "ACPI: * MADT\n");
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madt = (acpi_madt_t *) current;
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acpi_create_madt(madt);
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current += madt->header.length;
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ALIGN_CURRENT;
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acpi_add_table(rsdp, madt);
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printk(BIOS_DEBUG, "ACPI: * MCFG\n");
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mcfg = (acpi_mcfg_t *) current;
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acpi_create_mcfg(mcfg);
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current += mcfg->header.length;
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ALIGN_CURRENT;
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acpi_add_table(rsdp, mcfg);
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/* Pack GNVS into the ACPI table area */
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for (i=0; i < dsdt->length; i++) {
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if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
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printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
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"DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
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*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
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acpi_save_gnvs(current);
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break;
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}
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}
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/* And fill it */
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acpi_create_gnvs((global_nvs_t *)current);
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/* And tell SMI about it */
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#if CONFIG_HAVE_SMI_HANDLER
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smm_setup_structures((void *)current, NULL, NULL);
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#endif
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current += sizeof(global_nvs_t);
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ALIGN_CURRENT;
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/* We patched up the DSDT, so we need to recalculate the checksum */
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dsdt->checksum = 0;
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dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
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dsdt->length);
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#if CONFIG_HAVE_ACPI_SLIC
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printk(BIOS_DEBUG, "ACPI: * SLIC\n");
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slic = (acpi_header_t *)current;
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current += acpi_create_slic(current);
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ALIGN_CURRENT;
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acpi_add_table(rsdp, slic);
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#endif
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printk(BIOS_DEBUG, "ACPI: * SSDT\n");
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ssdt = (acpi_header_t *)current;
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acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
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current += ssdt->length;
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acpi_add_table(rsdp, ssdt);
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ALIGN_CURRENT;
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printk(BIOS_DEBUG, "current = %lx\n", current);
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printk(BIOS_INFO, "ACPI: done.\n");
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return current;
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}
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@ -21,6 +21,7 @@
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config NORTHBRIDGE_INTEL_FSP_RANGELEY
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bool
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select CPU_INTEL_FSP_MODEL_406DX
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select PER_DEVICE_ACPI_TABLES
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if NORTHBRIDGE_INTEL_FSP_RANGELEY
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@ -30,6 +30,8 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <build.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include "northbridge.h"
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unsigned long acpi_fill_mcfg(unsigned long current)
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@ -64,3 +66,15 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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return current;
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}
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void northbridge_acpi_fill_ssdt_generator(void)
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{
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u32 bmbound;
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char pscope[] = "\\_SB.PCI0";
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bmbound = sideband_read(B_UNIT, BMBOUND);
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acpigen_write_scope(pscope);
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acpigen_write_name_dword("BMBD", bmbound);
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acpigen_pop_len();
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generate_cpu_entries();
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}
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|
|
|||
|
|
@ -212,6 +212,18 @@ static void northbridge_enable(device_t dev)
|
|||
{
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_slit(unsigned long current)
|
||||
{
|
||||
// Not implemented
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_srat(unsigned long current)
|
||||
{
|
||||
/* No NUMA, no SRAT */
|
||||
return current;
|
||||
}
|
||||
|
||||
static struct pci_operations intel_pci_ops = {
|
||||
.set_subsystem = intel_set_subsystem,
|
||||
};
|
||||
|
|
@ -231,6 +243,7 @@ static struct device_operations mc_ops = {
|
|||
.set_resources = mc_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = northbridge_init,
|
||||
.acpi_fill_ssdt_generator = northbridge_acpi_fill_ssdt_generator,
|
||||
.enable = northbridge_enable,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &intel_pci_ops,
|
||||
|
|
|
|||
|
|
@ -72,6 +72,7 @@ void dump_pci_devices(void);
|
|||
void dump_spd_registers(void);
|
||||
void dump_mem(unsigned start, unsigned end);
|
||||
void report_platform_info(void);
|
||||
void northbridge_acpi_fill_ssdt_generator(void);
|
||||
|
||||
#endif /* #ifndef __ASSEMBLER__ */
|
||||
#endif /* #ifndef __ACPI__ */
|
||||
|
|
|
|||
|
|
@ -32,7 +32,8 @@ Name(\DSEN, 1) // Display Output Switching Enable
|
|||
*/
|
||||
|
||||
|
||||
OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00)
|
||||
External(NVSA)
|
||||
OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
|
||||
Field (GNVS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
/* Miscellaneous */
|
||||
|
|
|
|||
|
|
@ -31,8 +31,13 @@
|
|||
#include <arch/acpi.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <elog.h>
|
||||
#include <string.h>
|
||||
#include <cbmem.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include "soc.h"
|
||||
#include "irq.h"
|
||||
#include "nvs.h"
|
||||
|
||||
#define NMI_OFF 0
|
||||
|
||||
|
|
@ -426,6 +431,26 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
|||
}
|
||||
}
|
||||
|
||||
static void southbridge_inject_dsdt(void)
|
||||
{
|
||||
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
|
||||
|
||||
if (gnvs) {
|
||||
memset(gnvs, 0, sizeof(*gnvs));
|
||||
acpi_create_gnvs(gnvs);
|
||||
acpi_save_gnvs((unsigned long)gnvs);
|
||||
#if CONFIG_HAVE_SMI_HANDLER
|
||||
/* And tell SMI about it */
|
||||
smm_setup_structures(gnvs, NULL, NULL);
|
||||
#endif
|
||||
|
||||
/* Add it to DSDT. */
|
||||
acpigen_write_scope("\\");
|
||||
acpigen_write_name_dword("NVSA", (u32) gnvs);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
|
||||
static struct pci_operations pci_ops = {
|
||||
.set_subsystem = set_subsystem,
|
||||
};
|
||||
|
|
@ -435,6 +460,8 @@ static struct device_operations device_ops = {
|
|||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = soc_lpc_enable_resources,
|
||||
.init = lpc_init,
|
||||
.write_acpi_tables = acpi_write_hpet,
|
||||
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
|
||||
.enable = soc_lpc_enable,
|
||||
.scan_bus = scan_static_bus,
|
||||
.ops_pci = &pci_ops,
|
||||
|
|
|
|||
|
|
@ -149,6 +149,7 @@ typedef struct {
|
|||
|
||||
} __attribute__((packed)) global_nvs_t;
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t *gnvs);
|
||||
#ifdef __SMM__
|
||||
/* Used in SMM to find the ACPI GNVS address */
|
||||
global_nvs_t *smm_get_gnvs(void);
|
||||
|
|
|
|||
Loading…
Reference in New Issue