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make log message a little prettier 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo 2004-03-25 18:04:18 +00:00
parent edeff59c72
commit 68a5e08499
10 changed files with 300 additions and 302 deletions
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2
src/mainboard/amd/quartet/auto.c
View File

@ -217,7 +217,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0

2
src/mainboard/amd/solo/auto.c
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@ -116,7 +116,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0

27
src/mainboard/arima/hdama/auto.c
View File

@ -39,6 +39,10 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
} }
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static void memreset_setup(void) static void memreset_setup(void)
{ {
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
@ -46,8 +50,7 @@ static void memreset_setup(void)
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */ /* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} } else {
else {
/* Ensure the CPU has controll of the memory lines */ /* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
} }
@ -121,18 +124,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
#define FIRST_CPU 1 #define FIRST_CPU 1
#define SECOND_CPU 1 #define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(void) static void main(void)
{ {
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static const struct mem_controller cpu[] = { static const struct mem_controller cpu[] = {
#if FIRST_CPU #if FIRST_CPU
{ {
@ -157,40 +153,47 @@ static void main(void)
}, },
#endif #endif
}; };
int needs_reset; int needs_reset;
enable_lapic(); enable_lapic();
init_timer(); init_timer();
if (cpu_init_detected()) { if (cpu_init_detected()) {
asm("jmp __cpu_reset"); asm("jmp __cpu_reset");
} }
distinguish_cpu_resets(); distinguish_cpu_resets();
if (!boot_cpu()) { if (!boot_cpu()) {
stop_this_cpu(); stop_this_cpu();
} }
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
setup_default_resource_map(); setup_default_resource_map();
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0
print_pci_devices(); print_pci_devices();
#endif #endif
enable_smbus(); enable_smbus();
#if 0 #if 0
dump_spd_registers(&cpu[0]); dump_spd_registers(&cpu[0]);
#endif #endif
memreset_setup(); memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0 #if 0
dump_pci_devices(); dump_pci_devices();
#endif
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 2)); dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif #endif

2
src/mainboard/newisys/khepri/auto.c
View File

@ -171,7 +171,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0

2
src/mainboard/tyan/s2880/auto.c
View File

@ -166,7 +166,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\t");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2881/auto.c
View File

@ -165,7 +165,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\t");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2882/auto.c
View File

@ -172,7 +172,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0

38
src/mainboard/tyan/s2885/auto.c
View File

@ -1,5 +1,4 @@
#define ASSEMBLY 1 #define ASSEMBLY 1
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
@ -40,25 +39,24 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
} }
#define REV_B_RESET 0
static void memreset_setup(void) static void memreset_setup(void)
{ {
#if REV_B_RESET==1 if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
#else
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
#endif
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
} else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
} }
static void memreset(int controllers, const struct mem_controller *ctrl) static void memreset(int controllers, const struct mem_controller *ctrl)
{ {
if (is_cpu_pre_c0()) {
udelay(800); udelay(800);
#if REV_B_RESET==1
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
#endif
udelay(90); udelay(90);
} }
}
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
{ {
@ -96,7 +94,6 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
maxnodes = 2; maxnodes = 2;
} }
if (!(node >= maxnodes || row >= maxnodes)) { if (!(node >= maxnodes || row >= maxnodes)) {
ret = rows_2p[node][row]; ret = rows_2p[node][row];
} }
@ -166,24 +163,29 @@ static void main(void)
}, },
}; };
int needs_reset; int needs_reset;
enable_lapic(); enable_lapic();
init_timer(); init_timer();
if (cpu_init_detected()) { if (cpu_init_detected()) {
asm("jmp __cpu_reset"); asm("jmp __cpu_reset");
} }
distinguish_cpu_resets(); distinguish_cpu_resets();
if (!boot_cpu()) { if (!boot_cpu()) {
stop_this_cpu(); stop_this_cpu();
} }
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
setup_s2885_resource_map(); setup_s2885_resource_map();
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
// needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); // needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0])); needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0
@ -194,18 +196,19 @@ static void main(void)
#if 0 #if 0
print_pci_devices(); print_pci_devices();
#endif #endif
enable_smbus(); enable_smbus();
#if 0 #if 0
dump_spd_registers(&cpu[0]); dump_spd_registers(&cpu[0]);
#endif #endif
memreset_setup(); memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0 #if 1
dump_pci_devices(); dump_pci_devices();
#endif //dump_pci_device(PCI_DEV(0, 0x18, 1));
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 1));
#endif #endif
/* Check all of memory */ /* Check all of memory */
@ -216,11 +219,7 @@ static void main(void)
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo); print_debug_hex32(msr.lo);
print_debug("\r\n"); print_debug("\r\n");
#endif
/*
#if 0
ram_check(0x00000000, msr.lo+(msr.hi<<32)); ram_check(0x00000000, msr.lo+(msr.hi<<32));
#else
#if TOTAL_CPUS < 2 #if TOTAL_CPUS < 2
// Check 16MB of memory @ 0 // Check 16MB of memory @ 0
ram_check(0x00000000, 0x00100000); ram_check(0x00000000, 0x00100000);
@ -229,5 +228,4 @@ static void main(void)
ram_check(0x80000000, 0x80100000); ram_check(0x80000000, 0x80100000);
#endif #endif
#endif #endif
*/
} }

5
src/mainboard/tyan/s2885/resourcemap.c
View File

@ -254,13 +254,10 @@ static void setup_s2885_resource_map(void)
*/ */
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207, PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050007, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050007,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000203,
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050003,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x00000203,
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
}; };
int max; int max;
max = sizeof(register_values)/sizeof(register_values[0]); max = sizeof(register_values)/sizeof(register_values[0]);
setup_resource_map(register_values, max); setup_resource_map(register_values, max);

2
src/mainboard/tyan/s4880/auto.c
View File

@ -216,7 +216,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }