tegra132: Clean up clock register writes
Clean up functions to write to clk_enb and rst_dev registers and add clock_disable and clock_set_reset functions to provide a complete API for updating the registers. BUG=chrome-os-partner:31821 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles successfully on rush Change-Id: Ib0b7e3fc322f18be396ecf3b02b2399d4ba33e9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bb222adc22c7e26077dfb2ba6e4d41a4965d183 Original-Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219191 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9099 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
This commit is contained in:
Furquan Shaikh
Patrick Georgi
parent
cd72103021
commit
68a672c2c2
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@ -23,6 +23,7 @@
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#include <cbfs.h>
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#include <timer.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/cpu.h>
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#include <soc/romstage.h>
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#include "clk_rst.h"
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@ -109,16 +110,8 @@ int ccplex_load_mts(void)
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static void enable_cpu_clocks(void)
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{
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struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS;
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uint32_t reg;
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reg = read32(&clk_rst->clk_enb_l_set);
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reg |= CLK_ENB_CPU;
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write32(reg, &clk_rst->clk_enb_l_set);
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reg = read32(&clk_rst->clk_enb_v_set);
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reg |= SET_CLK_ENB_CPUG_ENABLE | SET_CLK_ENB_CPULP_ENABLE;
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write32(reg, &clk_rst->clk_enb_v_set);
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clock_enable(CLK_ENB_CPU, 0, 0, SET_CLK_ENB_CPUG_ENABLE |
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SET_CLK_ENB_CPULP_ENABLE, 0, 0);
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}
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static void enable_cpu_power_partitions(void)
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@ -151,7 +151,7 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
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u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */
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u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */
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u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */
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u32 clk_enb_u_clk; /* _CLK_ENB_U_CLR 0x334 */
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u32 clk_enb_u_clr; /* _CLK_ENB_U_CLR 0x334 */
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u32 _rsv22; /* 0x338 */
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u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */
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u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */
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@ -301,6 +301,12 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
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};
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check_member(clk_rst_ctlr, clk_src_i2c6, 0x65C);
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#define CLK_RST_REG(field_) \
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(&(((struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE)->field_))
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/* L, H, U, V, W, X */
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#define DEV_CONFIG_BLOCKS 6
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#define TEGRA_DEV_L 0
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#define TEGRA_DEV_H 1
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#define TEGRA_DEV_U 2
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@ -403,9 +403,8 @@ void clock_early_uart(void)
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write32(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT |
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CLK_UART_DIV_OVERRIDE |
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CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta);
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setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA);
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udelay(2);
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clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA);
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clock_enable_clear_reset_l(CLK_L_UARTA);
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}
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/* Enable output clock (CLK1~3) for external peripherals. */
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@ -593,36 +592,70 @@ void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg,
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writel(val, rst_dev_clr_reg);
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}
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void clock_enable(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
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static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = {
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CLK_RST_REG(clk_enb_l_set),
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CLK_RST_REG(clk_enb_h_set),
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CLK_RST_REG(clk_enb_u_set),
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CLK_RST_REG(clk_enb_v_set),
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CLK_RST_REG(clk_enb_w_set),
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CLK_RST_REG(clk_enb_x_set),
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};
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static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = {
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CLK_RST_REG(clk_enb_l_clr),
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CLK_RST_REG(clk_enb_h_clr),
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CLK_RST_REG(clk_enb_u_clr),
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CLK_RST_REG(clk_enb_v_clr),
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CLK_RST_REG(clk_enb_w_clr),
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CLK_RST_REG(clk_enb_x_clr),
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};
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static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = {
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CLK_RST_REG(rst_dev_l_set),
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CLK_RST_REG(rst_dev_h_set),
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CLK_RST_REG(rst_dev_u_set),
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CLK_RST_REG(rst_dev_v_set),
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CLK_RST_REG(rst_dev_w_set),
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CLK_RST_REG(rst_dev_x_set),
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};
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static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = {
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CLK_RST_REG(rst_dev_l_clr),
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CLK_RST_REG(rst_dev_h_clr),
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CLK_RST_REG(rst_dev_u_clr),
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CLK_RST_REG(rst_dev_v_clr),
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CLK_RST_REG(rst_dev_w_clr),
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CLK_RST_REG(rst_dev_x_clr),
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};
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static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS],
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u32 bits[DEV_CONFIG_BLOCKS])
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{
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if (l)
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writel(l, &clk_rst->clk_enb_l_set);
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if (h)
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writel(h, &clk_rst->clk_enb_h_set);
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if (u)
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writel(u, &clk_rst->clk_enb_u_set);
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if (v)
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writel(v, &clk_rst->clk_enb_v_set);
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if (w)
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writel(w, &clk_rst->clk_enb_w_set);
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if (x)
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writel(x, &clk_rst->clk_enb_x_set);
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int i = 0;
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for (; i < DEV_CONFIG_BLOCKS; i++)
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if (bits[i])
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writel(bits[i], regs[i]);
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}
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void clock_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
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void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS])
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{
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if (l)
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writel(l, &clk_rst->rst_dev_l_clr);
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if (h)
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writel(h, &clk_rst->rst_dev_h_clr);
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if (u)
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writel(u, &clk_rst->rst_dev_u_clr);
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if (v)
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writel(v, &clk_rst->rst_dev_v_clr);
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if (w)
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writel(w, &clk_rst->rst_dev_w_clr);
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if (x)
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writel(x, &clk_rst->rst_dev_x_clr);
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clock_write_regs(clk_enb_set_arr, bits);
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}
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void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS])
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{
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clock_write_regs(clk_enb_clr_arr, bits);
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}
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void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS])
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{
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clock_write_regs(rst_dev_set_arr, bits);
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}
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void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS])
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{
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clock_write_regs(rst_dev_clr_arr, bits);
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}
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void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
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@ -632,47 +665,48 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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clock_clear_reset(l, h, u, v, w, x);
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clock_clr_reset(l, h, u, v, w, x);
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}
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static void clock_reset_dev(u32 *setaddr, u32 *clraddr, u32 bit)
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{
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writel(bit, setaddr);
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udelay(LOGIC_STABILIZATION_DELAY);
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writel(bit, clraddr);
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}
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void clock_reset_l(u32 bit)
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{
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writel(bit, &clk_rst->rst_dev_l_set);
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udelay(1);
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writel(bit, &clk_rst->rst_dev_l_clr);
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clock_reset_dev(CLK_RST_REG(rst_dev_l_set), CLK_RST_REG(rst_dev_l_clr),
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bit);
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}
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void clock_reset_h(u32 bit)
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{
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writel(bit, &clk_rst->rst_dev_h_set);
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udelay(1);
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writel(bit, &clk_rst->rst_dev_h_clr);
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clock_reset_dev(CLK_RST_REG(rst_dev_h_set), CLK_RST_REG(rst_dev_h_clr),
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bit);
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}
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void clock_reset_u(u32 bit)
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{
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writel(bit, &clk_rst->rst_dev_u_set);
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udelay(1);
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writel(bit, &clk_rst->rst_dev_u_clr);
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clock_reset_dev(CLK_RST_REG(rst_dev_u_set), CLK_RST_REG(rst_dev_u_clr),
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bit);
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}
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void clock_reset_v(u32 bit)
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{
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writel(bit, &clk_rst->rst_dev_v_set);
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udelay(1);
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writel(bit, &clk_rst->rst_dev_v_clr);
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clock_reset_dev(CLK_RST_REG(rst_dev_v_set), CLK_RST_REG(rst_dev_v_clr),
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bit);
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}
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void clock_reset_w(u32 bit)
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{
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writel(bit, &clk_rst->rst_dev_w_set);
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udelay(1);
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writel(bit, &clk_rst->rst_dev_w_clr);
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clock_reset_dev(CLK_RST_REG(rst_dev_w_set), CLK_RST_REG(rst_dev_w_clr),
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bit);
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}
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void clock_reset_x(u32 bit)
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{
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writel(bit, &clk_rst->rst_dev_x_set);
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udelay(1);
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writel(bit, &clk_rst->rst_dev_x_clr);
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clock_reset_dev(CLK_RST_REG(rst_dev_x_set), CLK_RST_REG(rst_dev_x_clr),
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bit);
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}
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@ -47,9 +47,6 @@ enum {
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CLK_X_SET = 5,
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};
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#define CLK_RST_REG(field_) \
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&(((struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE)->field_)
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#define CLK_SET_REGS(x) \
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{ \
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CLK_RST_REG(clk_enb_##x##_set), \
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@ -53,8 +53,7 @@ static void remove_clamps(int id)
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static void enable_sor_periph_clocks(void)
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{
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setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_HOST1X);
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setbits_le32(&clk_rst->clk_out_enb_x, CLK_X_DPAUX);
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clock_enable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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@ -62,8 +61,7 @@ static void enable_sor_periph_clocks(void)
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static void disable_sor_periph_clocks(void)
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{
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clrbits_le32(&clk_rst->clk_out_enb_l, CLK_L_HOST1X);
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clrbits_le32(&clk_rst->clk_out_enb_x, CLK_X_DPAUX);
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clock_disable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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@ -71,8 +69,7 @@ static void disable_sor_periph_clocks(void)
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static void unreset_sor_periphs(void)
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{
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clrbits_le32(&clk_rst->rst_dev_l, CLK_L_HOST1X);
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clrbits_le32(&clk_rst->rst_dev_x, CLK_X_DPAUX);
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clock_clr_reset(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX);
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}
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void soc_configure_i2c6pad(void)
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@ -108,5 +105,5 @@ void soc_configure_i2c6pad(void)
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/* Stop Host1X/DPAUX clocks and reset Host1X */
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disable_sor_periph_clocks();
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setbits_le32(&clk_rst->rst_dev_l, CLK_L_HOST1X);
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clock_set_reset_l(CLK_L_HOST1X);
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}
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@ -226,6 +226,7 @@ enum {
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#define CLOCK_PLL_STABLE_DELAY_US 300
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#define IO_STABILIZATION_DELAY (2)
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#define LOGIC_STABILIZATION_DELAY (2)
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/* Calculate clock fractional divider value from ref and target frequencies.
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* This is for a U7.1 format. This is not well written up in the book and
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@ -301,6 +302,71 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
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#define TEGRA_PLLD_KHZ (925000)
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#define TEGRA_PLLU_KHZ (960000)
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#define clock_enable(l, h, u, v, w, x) \
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do { \
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u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x}; \
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clock_enable_regs(bits); \
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} while (0)
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#define clock_disable(l, h, u, v, w, x) \
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do { \
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u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x}; \
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clock_disable_regs(bits); \
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} while (0)
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#define clock_set_reset(l, h, u, v, w, x) \
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do { \
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u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x}; \
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clock_set_reset_regs(bits); \
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} while (0)
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#define clock_clr_reset(l, h, u, v, w, x) \
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do { \
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u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x}; \
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clock_clr_reset_regs(bits); \
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} while (0)
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#define clock_enable_l(l) clock_enable(l, 0, 0, 0, 0, 0)
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#define clock_enable_h(h) clock_enable(0, h, 0, 0, 0, 0)
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#define clock_enable_u(u) clock_enable(0, 0, u, 0, 0, 0)
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#define clock_enable_v(v) clock_enable(0, 0, 0, v, 0, 0)
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#define clock_enable_w(w) clock_enable(0, 0, 0, 0, w, 0)
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#define clock_enable_x(x) clock_enable(0, 0, 0, 0, 0, x)
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#define clock_disable_l(l) clock_disable(l, 0, 0, 0, 0, 0)
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#define clock_disable_h(h) clock_disable(0, h, 0, 0, 0, 0)
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#define clock_disable_u(u) clock_disable(0, 0, u, 0, 0, 0)
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#define clock_disable_v(v) clock_disable(0, 0, 0, v, 0, 0)
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#define clock_disable_w(w) clock_disable(0, 0, 0, 0, w, 0)
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#define clock_disable_x(x) clock_disable(0, 0, 0, 0, 0, x)
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#define clock_set_reset_l(l) clock_set_reset(l, 0, 0, 0, 0, 0)
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#define clock_set_reset_h(h) clock_set_reset(0, h, 0, 0, 0, 0)
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#define clock_set_reset_u(u) clock_set_reset(0, 0, u, 0, 0, 0)
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#define clock_set_reset_v(v) clock_set_reset(0, 0, 0, v, 0, 0)
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#define clock_set_reset_w(w) clock_set_reset(0, 0, 0, 0, w, 0)
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#define clock_set_reset_x(x) clock_set_reset(0, 0, 0, 0, 0, x)
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#define clock_clr_reset_l(l) clock_clr_reset(l, 0, 0, 0, 0, 0)
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#define clock_clr_reset_h(h) clock_clr_reset(0, h, 0, 0, 0, 0)
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#define clock_clr_reset_u(u) clock_clr_reset(0, 0, u, 0, 0, 0)
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#define clock_clr_reset_v(v) clock_clr_reset(0, 0, 0, v, 0, 0)
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#define clock_clr_reset_w(w) clock_clr_reset(0, 0, 0, 0, w, 0)
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#define clock_clr_reset_x(x) clock_clr_reset(0, 0, 0, 0, 0, x)
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#define clock_enable_clear_reset_l(l) \
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clock_enable_clear_reset(l, 0, 0, 0, 0, 0)
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#define clock_enable_clear_reset_h(h) \
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clock_enable_clear_reset(0, h, 0, 0, 0, 0)
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#define clock_enable_clear_reset_u(u) \
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clock_enable_clear_reset(0, 0, u, 0, 0, 0)
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#define clock_enable_clear_reset_v(v) \
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clock_enable_clear_reset(0, 0, 0, v, 0, 0)
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#define clock_enable_clear_reset_w(w) \
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clock_enable_clear_reset(0, 0, 0, 0, w, 0)
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#define clock_enable_clear_reset_x(x) \
|
||||
clock_enable_clear_reset(0, 0, 0, 0, 0, x)
|
||||
|
||||
int clock_get_osc_khz(void);
|
||||
int clock_get_pll_input_khz(void);
|
||||
u32 clock_display(u32 frequency);
|
||||
|
|
@ -311,8 +377,10 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
|
|||
u32 same_freq);
|
||||
void clock_cpu0_config(void);
|
||||
void clock_halt_avp(void);
|
||||
void clock_enable(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
|
||||
void clock_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
|
||||
void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS]);
|
||||
void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS]);
|
||||
void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]);
|
||||
void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]);
|
||||
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
|
||||
void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg);
|
||||
void clock_reset_l(u32 l);
|
||||
|
|
|
|||
Loading…
Reference in New Issue