nb/intel/ironlake: Simplify BAR handling
Currently, northbridge BARs are 32-bit values. We don't have any use case for BARs above 4 GiB in early stages, so handling possibly 64-bit values seems unnecessary, which currently is a noisy way to write zero. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -38,15 +38,11 @@ static void ironlake_setup_bars(void)
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printk(BIOS_DEBUG, "Setting up static northbridge registers...");
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/* Set up all hardcoded northbridge BARs */
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pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4,
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(0LL + DEFAULT_EPBAR) >> 32);
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pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0);
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pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4,
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(0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
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pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0);
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pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4,
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(0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32);
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pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0);
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
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