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mb/google/brya/var/marasov: Add the FIVR configurations 

This patch enables V1p05 and Vnn external bypass VRs for Marasov.

BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Frank Chu 2022-12-02 11:38:44 +08:00 committed by Felix Held
parent fa93c5bd01
commit 68bbbf8db2
1 changed files with 14 additions and 0 deletions
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14
src/mainboard/google/brya/variants/marasov/overridetree.cb
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@ -49,6 +49,20 @@ chip soc/intel/alderlake
}, },
}" }"
register "sagv" = "SaGv_Enabled" register "sagv" = "SaGv_Enabled"
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
FIVR_VOLTAGE_MIN_ACTIVE |
FIVR_VOLTAGE_MIN_RETENTION,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL |
FIVR_VOLTAGE_MIN_ACTIVE |
FIVR_VOLTAGE_MIN_RETENTION,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1250,
}"
register "serial_io_i2c_mode" = "{ register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
}" }"