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autoport: move spi_uvscc and spi_lvscc to devicetree.cb 

Change-Id: I36866cc793b3ddf9a78fed2e2840958d08327e7d
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Iru Cai 2017-07-07 13:49:08 +08:00 committed by Patrick Rudolph
parent 66f1f382cd
commit 68c7118266
1 changed files with 2 additions and 4 deletions
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6
util/autoport/bd82x6x.go
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@ -205,10 +205,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
/* SPI init */
MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h")
/* FIXME:XX Move this to runtime. */
for _, addr := range []uint16{0x38c8, 0x38c4} {
MainboardInit += fmt.Sprintf("\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr])
}
FADT := ctx.InfoSource.GetACPI()["FACP"]
@ -246,6 +242,8 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
"p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
"c2_latency": FormatHexLE16(FADT[96:98]),
"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4] &^ (1 << 23)),
},
PCISlots: []PCISlot{
PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},