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supermicro/x11-lga1151/gpio: 2/4 Exclude fields for PAD_CFG 

This patch excludes bit fields that should be ignored [1] in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:

./intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h

/intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h

[1] ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
    Disable (bit 9:8) for the native function, because it does not
    affect the pad in this mode.

This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":

CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG

Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42917
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov 2020-06-28 10:53:15 +03:00 committed by Michael Niewöhner
parent 97f69a1a94
commit 68c7eff5fe
2 changed files with 280 additions and 441 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

180
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
View File

@ -11,62 +11,62 @@ static const struct pad_config gpio_table[] = {
/* GPP_A0 - RCIN# */
/* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A0,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A1 - LAD0 */
/* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A1,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A2 - LAD1 */
/* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A2,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A3 - LAD2 */
/* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A3,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A4 - LAD3 */
/* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A4,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A5 - LFRAME# */
/* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A5,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A6 - SERIRQ */
/* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A6,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A7 - PIRQA# */
/* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A7,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A8 - CLKRUN# */
/* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A8,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A9 - CLKOUT_LPC0 */
/* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A9,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A10 - CLKOUT_LPC1 */
/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A10,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A11 - PME# */
/* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A11,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A12 - GPIO */
/* PAD_CFG_GPO(GPP_A12, 1, PLTRST), */
@ -76,22 +76,22 @@ static const struct pad_config gpio_table[] = {
/* GPP_A13 - SUSWARN# */
/* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A13,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A14 - SUS_STAT# */
/* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A14,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A15 - SUS_ACK# */
/* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A15,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A16 - CLKOUT_48 */
/* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A16,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A17 - GPIO */
/* PAD_NC(GPP_A17, NONE), */
@ -148,37 +148,37 @@ static const struct pad_config gpio_table[] = {
/* GPP_B4 - GPIO */
/* PAD_NC(GPP_B4, NONE), */
_PAD_CFG_STRUCT(GPP_B4,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B5 - GPIO */
/* PAD_NC(GPP_B5, NONE), */
_PAD_CFG_STRUCT(GPP_B5,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B6 - GPIO */
/* PAD_NC(GPP_B6, NONE), */
_PAD_CFG_STRUCT(GPP_B6,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B7 - GPIO */
/* PAD_NC(GPP_B7, NONE), */
_PAD_CFG_STRUCT(GPP_B7,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B8 - GPIO */
/* PAD_NC(GPP_B8, NONE), */
_PAD_CFG_STRUCT(GPP_B8,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B9 - GPIO */
/* PAD_NC(GPP_B9, NONE), */
_PAD_CFG_STRUCT(GPP_B9,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B10 - GPIO */
/* PAD_NC(GPP_B10, NONE), */
_PAD_CFG_STRUCT(GPP_B10,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_B11 - GPIO */
/* PAD_CFG_GPO(GPP_B11, 0, DEEP), */
@ -188,17 +188,17 @@ static const struct pad_config gpio_table[] = {
/* GPP_B12 - SLP_S0# */
/* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_B12,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B13 - PLTRST# */
/* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_B13,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B14 - SPKR */
/* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */
_PAD_CFG_STRUCT(GPP_B14,
PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
/* GPP_B15 - GPIO */
/* PAD_NC(GPP_B15, NONE), */
@ -243,7 +243,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_B23 - PCHHOT# */
/* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */
_PAD_CFG_STRUCT(GPP_B23,
PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF2) | PAD_RESET(DEEP), 0),
/* GPP_C0 - RESERVED */
@ -270,7 +270,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_C8 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_C8,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_C9 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), */
@ -280,7 +280,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_C10 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_C10,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_C11 - GPIO */
/* PAD_NC(GPP_C11, NONE), */
@ -300,7 +300,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_C14 - GPIO */
/* PAD_NC(GPP_C14, NONE), */
_PAD_CFG_STRUCT(GPP_C14,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_C15 - GPIO */
/* PAD_NC(GPP_C15, NONE), */
@ -340,18 +340,18 @@ static const struct pad_config gpio_table[] = {
/* GPP_C22 - GPIO */
/* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */
_PAD_CFG_STRUCT(GPP_C22,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE),
PAD_PULL(20K_PU)),
/* GPP_C23 - GPIO */
/* PAD_NC(GPP_C23, NONE), */
_PAD_CFG_STRUCT(GPP_C23,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D0 - GPIO */
/* PAD_NC(GPP_D0, NONE), */
_PAD_CFG_STRUCT(GPP_D0,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPP_D1 - GPIO */
/* PAD_CFG_GPO(GPP_D1, 1, DEEP), */
@ -361,7 +361,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_D2 - GPIO */
/* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */
_PAD_CFG_STRUCT(GPP_D2,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE),
PAD_PULL(20K_PU)),
/* GPP_D3 - GPIO */
@ -462,7 +462,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_D22 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_D22,
PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_D23 - GPIO */
/* PAD_NC(GPP_D23, NONE), */
@ -472,7 +472,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_E0 - SATAXPCIE0 */
/* PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E0,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E1 - GPIO */
/* PAD_NC(GPP_E1, NONE), */
@ -502,7 +502,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_E6 - GPIO */
/* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */
_PAD_CFG_STRUCT(GPP_E6,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE) | (1 << 1),
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE),
PAD_PULL(20K_PU)),
/* GPP_E7 - GPIO */
@ -513,27 +513,27 @@ static const struct pad_config gpio_table[] = {
/* GPP_E8 - SATA_LED# */
/* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E8,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E9 - USB_OC0# */
/* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E9,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E10 - USB_OC1# */
/* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E10,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E11 - USB_OC2# */
/* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E11,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E12 - USB_OC3# */
/* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_E12,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F0 - GPIO */
/* PAD_NC(GPP_F0, NONE), */
@ -563,7 +563,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_F5 - GPIO */
/* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */
_PAD_CFG_STRUCT(GPP_F5,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0),
/* GPP_F6 - GPIO */
/* PAD_CFG_GPO(GPP_F6, 1, PLTRST), */
@ -583,27 +583,27 @@ static const struct pad_config gpio_table[] = {
/* GPP_F9 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_F9,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_F10 - SATA_SCLOCK */
/* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F10,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F11 - SATA_SLOAD */
/* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F11,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F12 - SATA_SDATAOUT1 */
/* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F12,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F13 - SATA_SDATAOUT2 */
/* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F13,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F14 - GPIO */
/* PAD_NC(GPP_F14, NONE), */
@ -613,12 +613,12 @@ static const struct pad_config gpio_table[] = {
/* GPP_F15 - USB_OC4# */
/* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F15,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F16 - USB_OC5# */
/* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_F16,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F17 - GPIO */
/* PAD_NC(GPP_F17, NONE), */
@ -668,12 +668,12 @@ static const struct pad_config gpio_table[] = {
/* GPP_G2 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_G2,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_G3 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_G3,
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_G4 - GPIO */
/* PAD_NC(GPP_G4, NONE), */
@ -728,7 +728,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_G14 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_G14,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_G15 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), */
@ -748,12 +748,12 @@ static const struct pad_config gpio_table[] = {
/* GPP_G18 - NMI# */
/* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_G18,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G19 - SMI# */
/* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_G19,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G20 - GPIO */
/* PAD_NC(GPP_G20, NONE), */
@ -783,7 +783,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_H1 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_H1,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_H2 - GPIO */
/* PAD_CFG_GPO(GPP_H2, 1, DEEP), */
@ -793,12 +793,12 @@ static const struct pad_config gpio_table[] = {
/* GPP_H3 - SRCCLKREQ9# */
/* PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H3,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H4 - GPIO */
/* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), */
_PAD_CFG_STRUCT(GPP_H4,
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
/* GPP_H5 - GPIO */
/* PAD_CFG_GPO(GPP_H5, 1, PLTRST), */
@ -828,12 +828,12 @@ static const struct pad_config gpio_table[] = {
/* GPP_H10 - SML2CLK */
/* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H10,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H11 - SML2DATA */
/* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H11,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H12 - GPIO */
/* PAD_NC(GPP_H12, NONE), */
@ -843,12 +843,12 @@ static const struct pad_config gpio_table[] = {
/* GPP_H13 - SML3CLK */
/* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H13,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H14 - SML3DATA */
/* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H14,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H15 - GPIO */
/* PAD_NC(GPP_H15, NONE), */
@ -858,12 +858,12 @@ static const struct pad_config gpio_table[] = {
/* GPP_H16 - SML4CLK */
/* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H16,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H17 - SML4DATA */
/* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_H17,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_H18 - GPIO */
/* PAD_NC(GPP_H18, NONE), */
@ -908,37 +908,37 @@ static const struct pad_config gpio_table[] = {
/* GPD2 - LAN_WAKE# */
/* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD2,
PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1), 0),
/* GPD3 - PWRBTN# */
/* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD3,
PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1), 0),
/* GPD4 - SLP_S3# */
/* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD4,
PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1), 0),
/* GPD5 - SLP_S4# */
/* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD5,
PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1), 0),
/* GPD6 - SLP_A# */
/* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD6,
PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1), 0),
/* GPD7 - GPIO */
/* PAD_NC(GPD7, NONE), */
_PAD_CFG_STRUCT(GPD7,
PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0),
PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
/* GPD8 - SUSCLK */
/* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */
_PAD_CFG_STRUCT(GPD8,
PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1), 0),
/* GPD9 - GPIO */
/* PAD_NC(GPD9, NONE), */
@ -958,22 +958,22 @@ static const struct pad_config gpio_table[] = {
/* GPP_I0 - DDPB_HPD0 */
/* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I0,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I1 - DDPC_HPD1 */
/* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I1,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I2 - DDPD_HPD2 */
/* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I2,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I3 - DDPE_HPD3 */
/* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */
_PAD_CFG_STRUCT(GPP_I3,
PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),
/* GPP_I4 - GPIO */
/* PAD_NC(GPP_I4, NONE), */
@ -983,32 +983,32 @@ static const struct pad_config gpio_table[] = {
/* GPP_I5 - DDPB_CTRLCLK */
/* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I5,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I6 - DDPB_CTRLDATA */
/* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I6,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I7 - DDPC_CTRLCLK */
/* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I7,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I8 - DDPC_CTRLDATA */
/* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I8,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I9 - DDPD_CTRLCLK */
/* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I9,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_I10 - DDPD_CTRLDATA */
/* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_I10,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
};
@ -1020,47 +1020,47 @@ static const struct pad_config early_gpio_table[] = {
/* GPP_A1 - LAD0 */
/* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A1,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A2 - LAD1 */
/* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A2,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A3 - LAD2 */
/* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A3,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A4 - LAD3 */
/* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A4,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A5 - LFRAME# */
/* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A5,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A6 - SERIRQ */
/* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A6,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A8 - CLKRUN# */
/* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A8,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A9 - CLKOUT_LPC0 */
/* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A9,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A10 - CLKOUT_LPC1 */
/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
_PAD_CFG_STRUCT(GPP_A10,
PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
};
#endif /* _GPIO_X11SSH_TF_H */

541
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
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