LiPPERT Toucan-AF [2/2]: actually implement mainboard support
Step 2: change the Persimmon code to adapt it to the new board's hardware.
The Toucan-AF is a COM Express Compact Type 6 form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU
- 1-4 GB DDR3 memory down
- 1x VGA, 2x DisplayPort (1 switchable to LVDS)
- AMD A55E (Hudson-E1) southbridge
- 8x USB 2.0
- 4x SATA
- HD Audio (with codec on baseboard)
- NEC uPD78F0532 microcontroller on I2C ("SEMA")
- 7x PCIe2.0 x1 (1 on PEG)
- Intel I210 GbE (on APU PCIe x1, can be disabled for additional PCIe)
- 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS)
The Toucan-AF has no SIO on board. This patch includes basic support for a
Winbond W83627DHG (PS/2, 2x RS232), because the ADLINK ExpressBase-6 used
for evaluation happens to have one. The code may have to be adapted to the
actual baseboard of the application.
http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132
Change-Id: I9041b905bad45852ac9b402fcbd5decbc98b377b
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2572
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jens Rottmann
Stefan Reinauer
parent
1664404652
commit
68c9f2bdc5
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@ -15,10 +15,12 @@ config BOARD_LIPPERT_ROADRUNNER_LX
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bool "Cool RoadRunner-LX"
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config BOARD_LIPPERT_SPACERUNNER_LX
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bool "Cool SpaceRunner-LX"
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config BOARD_LIPPERT_TOUCAN_AF
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bool "Toucan-AF (+W83627DHG SIO)"
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endchoice
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if BOARD_LIPPERT_FRONTRUNNER_AF
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if BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF
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# No code, but two Kconfig options need to know this ...
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choice
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prompt "AMD Fusion CPU model"
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@ -47,7 +49,7 @@ config FUSION_G_T56N
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If unsure check with "grep model /proc/cpuinfo".
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endchoice
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endif # BOARD_LIPPERT_FRONTRUNNER_AF
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endif # BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF
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source "src/mainboard/lippert/frontrunner/Kconfig"
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source "src/mainboard/lippert/frontrunner-af/Kconfig"
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@ -55,6 +57,7 @@ source "src/mainboard/lippert/hurricane-lx/Kconfig"
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source "src/mainboard/lippert/literunner-lx/Kconfig"
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source "src/mainboard/lippert/roadrunner-lx/Kconfig"
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source "src/mainboard/lippert/spacerunner-lx/Kconfig"
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source "src/mainboard/lippert/toucan-af/Kconfig"
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config MAINBOARD_VENDOR
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string
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@ -22,7 +22,6 @@
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#include "dimmSpd.h"
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#include "BiosCallOuts.h"
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#include "heapManager.h"
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#include "SB800.h"
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STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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@ -445,9 +444,25 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt
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/* Call the host environment interface to provide a user hook opportunity. */
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AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
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// Make sure the right speed settings are selected.
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((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
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MEM_DATA_STRUCT *MemData = ConfigPtr;
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printk(BIOS_INFO, "Setting DDR3 voltage: ");
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FCH_IOMUX(65) = 1; // GPIO65: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V
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switch (MemData->ParameterListPtr->DDR3Voltage) {
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case VOLT1_25: // board is not able to provide this
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MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry
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printk(BIOS_INFO, "can't provide 1.25 V, using ");
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// fall through
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default: // AGESA.h says in mixed case 1.5V DIMMs get excluded
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case VOLT1_35:
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FCH_GPIO(65) = 0x08; // = output, disable PU, set to 0
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printk(BIOS_INFO, "1.35 V\n");
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break;
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case VOLT1_5:
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FCH_GPIO(65) = 0xC8; // = output, disable PU, set to 1
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printk(BIOS_INFO, "1.5 V\n");
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}
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return AGESA_SUCCESS;
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}
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@ -465,45 +480,7 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf
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/* PCIE slot reset control */
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AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status;
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UINTN FcnData;
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PCIe_SLOT_RESET_INFO *ResetInfo;
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UINT32 GpioMmioAddr;
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UINT32 AcpiMmioAddr;
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UINT8 Data8;
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UINT16 Data16;
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FcnData = Data;
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ResetInfo = ConfigPtr;
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// Get SB800 MMIO Base (AcpiMmioAddr)
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WriteIo8(0xCD6, 0x27);
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Data8 = ReadIo8(0xCD7);
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Data16=Data8<<8;
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WriteIo8(0xCD6, 0x26);
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Data8 = ReadIo8(0xCD7);
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Data16|=Data8;
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AcpiMmioAddr = (UINT32)Data16 << 16;
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Status = AGESA_UNSUPPORTED;
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GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
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switch (ResetInfo->ResetId)
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{
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case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
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switch (ResetInfo->ResetControl) {
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case AssertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
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Data8 &= ~(UINT8)BIT6 ;
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Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
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Status = AGESA_SUCCESS;
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break;
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case DeassertSlotReset:
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Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
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Data8 |= BIT6 ;
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Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
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Status = AGESA_SUCCESS;
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break;
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}
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break;
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}
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return Status;
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// COM Express doesn't provide dedicated resets for individual lanes
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// and it's not needed for the on-board Intel I210 GbE controller.
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return AGESA_UNSUPPORTED;
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}
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@ -22,6 +22,7 @@
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#include "Porting.h"
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#include "AGESA.h"
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#include "SB800.h"
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#define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */
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#define BIOS_HEAP_SIZE 0x20000
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@ -70,4 +71,13 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf
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/* PCIE slot reset control */
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AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
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/* FCH GPIO access helpers */
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#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr)))
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#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr)))
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#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr)))
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static inline u8 fch_gpio_state(unsigned int gpio_nr)
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{
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return FCH_GPIO(gpio_nr) >> 7;
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}
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#endif //_BIOS_CALLOUT_H_
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@ -17,7 +17,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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if BOARD_AMD_PERSIMMON
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if BOARD_LIPPERT_TOUCAN_AF
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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@ -26,11 +26,17 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_FINTEK_F81865F
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# The Toucan-AF is meant to work on any COM Express Type 6 baseboard.
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# The ADLINK ExpressBase-6 baseboard happens to use this SIO:
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select SUPERIO_WINBOND_W83627DHG
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_RESUME
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# S3 doesn't work yet, heapManager.c:576 failed last time I tried,
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# couldn't figure out why. But s3_resume.c (look for "spi_flash_probe")
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# erases 28 KB and writes 10 KB register dumps to SPI flash on every
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# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
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#select HAVE_ACPI_RESUME
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select HAVE_HARD_RESET
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select LIFT_BSP_APIC_ID
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@ -42,7 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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config MAINBOARD_DIR
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string
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default amd/persimmon
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default lippert/toucan-af
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config APIC_ID_OFFSET
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hex
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@ -50,7 +56,7 @@ config APIC_ID_OFFSET
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config MAINBOARD_PART_NUMBER
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string
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default "Persimmon"
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default "Toucan-AF"
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config HW_MEM_HOLE_SIZEK
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hex
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@ -58,7 +64,8 @@ config HW_MEM_HOLE_SIZEK
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config MAX_CPUS
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int
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default 2
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default 1 if FUSION_G_T40R
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default 2 if FUSION_G_T56N
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config MAX_PHYSICAL_CPUS
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int
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@ -111,7 +118,8 @@ config VGA_BIOS
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config VGA_BIOS_ID
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string
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default "1002,9802"
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default "1002,9804" if FUSION_G_T40R
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default "1002,9806" if FUSION_G_T56N
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config SB800_AHCI_ROM
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bool
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@ -121,4 +129,4 @@ config DRIVERS_PS2_KEYBOARD
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bool
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default n
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endif # BOARD_AMD_PERSIMMON
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endif # BOARD_LIPPERT_TOUCAN_AF
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@ -60,19 +60,19 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
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{
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0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
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},
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// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
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{
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0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
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},
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// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
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{
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0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
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PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
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},
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// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
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{
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@ -94,14 +94,14 @@ PCIe_DDI_DESCRIPTOR DdiList [] = {
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0, //Descriptor flags
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
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//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
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{ConnectorTypeLvds, Aux1, Hdp1}
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{ConnectorTypeAutoDetect, Aux1, Hdp1}
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},
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// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
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{
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DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
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//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
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{ConnectorTypeDP, Aux2, Hdp2}
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{ConnectorTypeAutoDetect, Aux2, Hdp2}
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}
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};
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@ -50,7 +50,7 @@
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#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
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//GNB GPP Port7
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#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable
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#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
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#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
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#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
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#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
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@ -0,0 +1,39 @@
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/*
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* SuperI/O devices
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*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 LiPPERT ADLINK Technology GmbH
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* (Written by Jens Rottmann <JRottmann@LiPPERTembedded.de> for LiPPERT)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* PS/2 Keyboard */
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Device(KBC) {
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Name(_HID, EISAID("PNP0303"))
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x0060, 0x0060, 1, 1)
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IO(Decode16, 0x0064, 0x0064, 1, 1)
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IRQNoFlags(){1}
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})
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}
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/* PS/2 Mouse */
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Device(PS2M) {
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Name(_HID, EISAID("PNP0F13"))
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Name(_CRS, ResourceTemplate() {
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IRQNoFlags(){12}
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})
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}
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@ -385,6 +385,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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// Byte6Seed, Byte7Seed, ByteEccSeed)
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// Specifies the write leveling seed for a channel of a socket.
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//
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HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
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PSO_END
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@ -29,10 +29,11 @@ chip northbridge/amd/agesa/family14/root_complex
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chip northbridge/amd/agesa/family14 # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
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device pci 4.0 on end # PCIE P2P bridge on-board NIC
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device pci 5.0 off end # PCIE P2P bridge
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device pci 6.0 on end # PCIE P2P bridge PCIe slot
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device pci 7.0 off end # PCIE P2P bridge
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#device pci 1.1 on end # Internal HDMI Audio
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device pci 4.0 on end # PCIE P2P bridge
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device pci 5.0 on end # PCIE P2P bridge
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device pci 6.0 on end # PCIE P2P bridge
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device pci 7.0 on end # PCIE P2P bridge on-board NIC
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device pci 8.0 off end # NB/SB Link P2P bridge
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end # agesa northbridge
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@ -47,97 +48,51 @@ chip northbridge/amd/agesa/family14/root_complex
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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device i2c 51 off end
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end
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end # SM
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device pci 14.1 on end # IDE 0x439c
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device pci 14.1 off end # IDE 0x439c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on # LPC 0x439d
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chip superio/fintek/f81865f
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device pnp 4e.0 off # Floppy
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io 0x60 = 0x3f0
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||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 4e.3 off end # Parallel Port
|
||||
device pnp 4e.4 off end # Hardware Monitor
|
||||
device pnp 4e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 4e.6 off end # GPIO
|
||||
device pnp 4e.a off end # PME
|
||||
device pnp 4e.10 on # COM1
|
||||
chip superio/winbond/w83627dhg
|
||||
device pnp 4e.0 off end # Floppy
|
||||
device pnp 4e.1 off end # Parallel Port
|
||||
device pnp 4e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 4e.11 on # COM2
|
||||
device pnp 4e.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
end # f81865f
|
||||
device pnp 4e.5 on # Keyboard, Mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
#device pnp 4e.6 off end # SPI
|
||||
device pnp 4e.307 off end # GPIO6
|
||||
device pnp 4e.8 off end # WDTO, PLED
|
||||
device pnp 4e.009 off end # GPIO2
|
||||
device pnp 4e.109 off end # GPIO3
|
||||
device pnp 4e.209 off end # GPIO4
|
||||
device pnp 4e.309 off end # GPIO5
|
||||
device pnp 4e.A off end # ACPI
|
||||
device pnp 4e.B off end # HW Monitor
|
||||
end # w83627dhg
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
|
||||
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
|
||||
device pci 14.5 off end # OHCI FS/LS USB
|
||||
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
|
||||
device pci 15.0 off end # PCIe PortA
|
||||
device pci 15.1 off end # PCIe PortB
|
||||
device pci 15.2 off end # PCIe PortC
|
||||
device pci 15.3 off end # PCIe PortD
|
||||
device pci 15.0 on end # PCIe PortA
|
||||
device pci 15.1 on end # PCIe PortB
|
||||
device pci 15.2 on end # PCIe PortC
|
||||
device pci 15.3 on end # PCIe PortD
|
||||
device pci 16.0 off end # OHCI USB 10-13
|
||||
device pci 16.2 off end # EHCI USB 10-13
|
||||
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
|
||||
register "gpp_configuration" = "4" #1:1:1:1
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
|
||||
#set up SB800 Fan control registers and IMC fan controls
|
||||
register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
|
||||
register "fan0_enabled" = "1"
|
||||
register "fan1_enabled" = "1"
|
||||
register "imc_fan_zone0_enabled" = "1"
|
||||
register "imc_fan_zone1_enabled" = "1"
|
||||
|
||||
register "fan0_config_vals" = "{ \
|
||||
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
|
||||
FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
|
||||
register "fan1_config_vals" = "{ \
|
||||
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
|
||||
FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
|
||||
|
||||
register "imc_zone0_mode1" = " \
|
||||
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
|
||||
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
|
||||
register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
|
||||
IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
|
||||
register "imc_zone0_temp_offset" = "0x00" # No temp offset
|
||||
register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis
|
||||
register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address
|
||||
register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
|
||||
register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate
|
||||
register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping
|
||||
|
||||
register "imc_zone1_mode1" = " \
|
||||
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
|
||||
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
|
||||
register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
|
||||
IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
|
||||
register "imc_zone1_temp_offset" = "0x00" # No temp offset
|
||||
register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis
|
||||
register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address
|
||||
register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
|
||||
register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate
|
||||
register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping
|
||||
|
||||
# T56N has a Maximum operating temperature of 90C
|
||||
# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
|
||||
# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
|
||||
register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
|
||||
register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }"
|
||||
register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }"
|
||||
register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }"
|
||||
|
||||
end #southbridge/amd/cimx/sb800
|
||||
# end # device pci 18.0
|
||||
# These seem unnecessary
|
||||
|
|
|
|||
|
|
@ -1462,6 +1462,7 @@ DefinitionBlock (
|
|||
}
|
||||
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
|
||||
#endif
|
||||
#include "acpi/superio.asl"
|
||||
} /* end LIBR */
|
||||
|
||||
Device(HPBR) {
|
||||
|
|
@ -1477,6 +1478,7 @@ DefinitionBlock (
|
|||
} /* end Ac97modem */
|
||||
|
||||
Name(CRES, ResourceTemplate() {
|
||||
IO(Decode16, 0x004E, 0x004E, 1, 2) /* SIO config regs */
|
||||
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
|
||||
|
||||
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
|
|
@ -29,6 +30,76 @@
|
|||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include "SBPLATFORM.h"
|
||||
#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
|
||||
|
||||
/* Write data block to slave on SMBUS0. */
|
||||
#define SMB0_STATUS ((SMBUS0_BASE_ADDRESS) + 0)
|
||||
#define SMB0_CONTROL ((SMBUS0_BASE_ADDRESS) + 2)
|
||||
#define SMB0_HOSTCMD ((SMBUS0_BASE_ADDRESS) + 3)
|
||||
#define SMB0_ADDRESS ((SMBUS0_BASE_ADDRESS) + 4)
|
||||
#define SMB0_DATA0 ((SMBUS0_BASE_ADDRESS) + 5)
|
||||
#define SMB0_BLOCKDATA ((SMBUS0_BASE_ADDRESS) + 7)
|
||||
static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data)
|
||||
{
|
||||
__outbyte(SMB0_STATUS, 0x1E); // clear error status
|
||||
__outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction=out
|
||||
__outbyte(SMB0_HOSTCMD, command); // or destination offset
|
||||
__outbyte(SMB0_DATA0, length); // sent before data
|
||||
__inbyte(SMB0_CONTROL); // reset block data array
|
||||
while (length--)
|
||||
__outbyte(SMB0_BLOCKDATA, *(data++));
|
||||
__outbyte(SMB0_CONTROL, 0x54); // execute block write, no IRQ
|
||||
|
||||
while (__inbyte(SMB0_STATUS) == 0x01) ; // busy, no errors
|
||||
return __inbyte(SMB0_STATUS) ^ 0x02; // 0x02 = completed, no errors
|
||||
}
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
int i;
|
||||
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
|
||||
|
||||
/* Init Hudson GPIOs. */
|
||||
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
|
||||
FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
|
||||
FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
|
||||
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS#
|
||||
FCH_GPIO (197) = 0x28; // = input, disable int. pull-up
|
||||
FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
|
||||
FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
|
||||
FCH_IOMUX( 57) = 1;
|
||||
FCH_GPIO ( 57) = 0x28;
|
||||
FCH_IOMUX( 58) = 1;
|
||||
FCH_GPIO ( 58) = 0x28;
|
||||
FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector
|
||||
FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0
|
||||
FCH_IOMUX(188) = 2;
|
||||
FCH_GPIO (188) = 0x08;
|
||||
FCH_IOMUX(166) = 2;
|
||||
FCH_GPIO (166) = 0x08;
|
||||
// needed to make GPO160 work (Hudson Register Reference section 2.3.6.1)
|
||||
FCH_PMIO(0xDC) &= ~0x80; FCH_PMIO(0xE6) = (FCH_PMIO(0xE6) & ~0x02) | 0x01;
|
||||
FCH_IOMUX(160) = 1;
|
||||
FCH_GPIO (160) = 0x08;
|
||||
FCH_IOMUX(189) = 1; // GPIO189-192: GPI0-3 on COM Express connector
|
||||
FCH_IOMUX(190) = 1; // default to inputs with int. PU
|
||||
FCH_IOMUX(191) = 1;
|
||||
FCH_IOMUX(192) = 1;
|
||||
if (!fch_gpio_state(197)) // just in case anyone cares
|
||||
printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
|
||||
printk(BIOS_INFO, "Board revision ID: %u\n",
|
||||
fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
|
||||
|
||||
/* Notify the SMC we're alive and kicking, or after a while it will
|
||||
* effect a power cycle and switch to the alternate BIOS chip.
|
||||
* Should be done as late as possible. */
|
||||
printk(BIOS_INFO, "Sending BIOS alive message\n");
|
||||
const u8 i_am_alive[] = { 0x03 }; //bit2=SEL_DP0: 0=DDI2, 1=LVDS
|
||||
if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive)))
|
||||
printk(BIOS_ERR, "smb_write_blk failed: %d\n", i);
|
||||
|
||||
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
|
||||
}
|
||||
|
||||
void set_pcie_reset(void);
|
||||
void set_pcie_dereset(void);
|
||||
|
|
@ -56,6 +127,7 @@ void set_pcie_dereset(void)
|
|||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
dev->ops->init = init;
|
||||
|
||||
/*
|
||||
* The mainboard is the first place that we get control in ramstage. Check
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@
|
|||
* Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
|
||||
* Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
|
||||
*/
|
||||
#define USB_CONFIG 0x7F
|
||||
#define USB_CONFIG 0x0F
|
||||
|
||||
/**
|
||||
* @def PCI_CLOCK_CTRL
|
||||
|
|
@ -90,7 +90,7 @@
|
|||
* PCI SLOT 3 define at BIT3
|
||||
* PCI SLOT 4 define at BIT4
|
||||
*/
|
||||
#define PCI_CLOCK_CTRL 0x07
|
||||
#define PCI_CLOCK_CTRL 0x1E
|
||||
|
||||
/**
|
||||
* @def SATA_CONTROLLER
|
||||
|
|
@ -180,7 +180,6 @@
|
|||
* SDIN2 is define at BIT4 & BIT5
|
||||
* SDIN3 is define at BIT6 & BIT7
|
||||
*/
|
||||
//#define AZALIA_SDIN_PIN 0xAA
|
||||
#define AZALIA_SDIN_PIN 0x2A
|
||||
|
||||
/**
|
||||
|
|
@ -225,29 +224,32 @@
|
|||
* 0 - Enable
|
||||
* 1 - Disable
|
||||
*/
|
||||
#define GEC_CONFIG 0
|
||||
#define GEC_CONFIG 1
|
||||
|
||||
static const CODECENTRY persimmon_codec_alc269[] =
|
||||
static const CODECENTRY sample_codec_alc886[] = /* Realtek ALC886/8 */
|
||||
{
|
||||
/* NID, PinConfig */
|
||||
{0x12, 0x411111F0},
|
||||
{0x14, 0x99130110},
|
||||
{0x21, 0x0121401F},
|
||||
{0x17, 0x411111F0},
|
||||
{0x18, 0x01A19820},
|
||||
{0x19, 0x411111F0},
|
||||
{0x1A, 0x0181302F},
|
||||
{0x1B, 0x411111F0},
|
||||
{0x1D, 0x40069E05},
|
||||
{0x1E, 0x411111F0},
|
||||
{0x20, 0x0001FFFF},
|
||||
/* NID, PinConfig (Verbs 71F..C) */
|
||||
{0x11, 0x411111F0}, /* NPC */
|
||||
{0x12, 0x411111F0}, /* DMIC */
|
||||
{0x14, 0x01214110}, /* FRONT (Port-D) */
|
||||
{0x15, 0x01011112}, /* SURR (Port-A) */
|
||||
{0x16, 0x01016111}, /* CEN/LFE (Port-G) */
|
||||
{0x17, 0x411111F0}, /* SIDESURR (Port-H) */
|
||||
{0x18, 0x01A19930}, /* MIC1 (Port-B) */
|
||||
{0x19, 0x411111F0}, /* MIC2 (Port-F) */
|
||||
{0x1A, 0x0181313F}, /* LINE1 (Port-C) */
|
||||
{0x1B, 0x411111F0}, /* LINE2 (Port-E) */
|
||||
{0x1C, 0x411111F0}, /* CD-IN */
|
||||
{0x1D, 0x40132601}, /* BEEP-IN */
|
||||
{0x1E, 0x01441120}, /* S/PDIF-OUT */
|
||||
{0x1F, 0x01C46140}, /* S/PDIF-IN */
|
||||
{0xff, 0xffffffff} /* end of table */
|
||||
};
|
||||
|
||||
static const CODECTBLLIST codec_tablelist[] =
|
||||
{
|
||||
{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
|
||||
{0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
|
||||
{0x10ec0888, (CODECENTRY*)&sample_codec_alc886[0]},
|
||||
{0xFFFFFFFF, (CODECENTRY*)0xFFFFFFFFL}
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
#include <console/loglevel.h>
|
||||
#include "agesawrapper.h"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "superio/fintek/f81865f/f81865f_early_serial.c"
|
||||
#include "superio/winbond/w83627dhg/w83627dhg.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "drivers/pc80/i8254.c"
|
||||
#include "drivers/pc80/i8259.c"
|
||||
|
|
@ -45,7 +45,7 @@
|
|||
void disable_cache_as_ram(void); /* cache_as_ram.inc */
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
|
||||
#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
|
|
@ -70,7 +70,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
sb_Poweron_Init();
|
||||
|
||||
post_code(0x31);
|
||||
f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue