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soc/mediatek/mt8192: Save dramc shuffle result after calibration 

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Huayang Duan 2020-06-24 09:11:24 +08:00 committed by Hung-Te Lin
parent 7ce9883058
commit 68cb9ed068
2 changed files with 89 additions and 0 deletions
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84
src/soc/mediatek/mt8192/dramc_dvfs.c
View File

@ -104,3 +104,87 @@ void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level)
pll_mode = !pll_mode;
*(cali->pll_mode) = pll_mode;
}
void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst)
{
u8 tmp;
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_APB_SLV_SEL, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SRAM_WR_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_APB_WR_MODE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, src);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, dst);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 1);
do {
tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
MISC_DMA_DEBUG0_SRAM_DONE);
tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
MISC_DMA_DEBUG0_APB_DONE) << 1);
dramc_dbg("Waiting dramc to shuffle sram, tmp: %u\n", tmp);
} while (tmp != 0x3);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_MODE, 0);
}
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SRAM_WR_MODE, 0);
}
void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst)
{
u8 tmp;
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_APB_SLV_SEL, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SRAM_WR_MODE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_APB_WR_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, dst);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, src);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 1);
do {
tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
MISC_DMA_DEBUG0_SRAM_DONE);
tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
MISC_DMA_DEBUG0_APB_DONE) << 1);
dramc_dbg("Waiting shuffle sram to dramc, tmp: %u\n", tmp);
} while (tmp != 0x3);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_MODE, 0);
}
}

5
src/soc/mediatek/mt8192/dramc_pi_main.c
View File

@ -321,6 +321,11 @@ void init_dram(const struct dramc_data *dparam)
get_dram_info_after_cal(&cali);
dramc_ac_timing_optimize(&cali);
dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu);
/* for frequency switch in dramc_mode_reg_init phase */
if (first_freq_k)
dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1);
first_freq_k = false;
}