soc/intel/skylake: Drop always-zero ProbelessTrace dt setting

This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.

Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/51nb/x210/devicetree.cb

@@ -32,7 +32,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "1"
 	register "SataMode" = "0"
 

src/mainboard/google/eve/devicetree.cb

@@ -35,7 +35,6 @@ chip soc/intel/skylake
 	register "gen3_dec" = "0x00fc0901"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/mainboard/google/fizz/variants/baseboard/devicetree.cb

@@ -64,7 +64,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "1"

src/mainboard/google/glados/devicetree.cb

@@ -34,7 +34,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/mainboard/google/poppy/variants/atlas/devicetree.cb

@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/mainboard/google/poppy/variants/baseboard/devicetree.cb

@@ -31,7 +31,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/mainboard/google/poppy/variants/nami/devicetree.cb

@@ -31,7 +31,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "DspEnable" = "1"

src/mainboard/google/poppy/variants/nautilus/devicetree.cb

@@ -31,7 +31,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/mainboard/google/poppy/variants/nocturne/devicetree.cb

@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/mainboard/google/poppy/variants/rammus/devicetree.cb

@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/mainboard/google/poppy/variants/soraka/devicetree.cb

@@ -31,7 +31,6 @@ chip soc/intel/skylake
 	register "s0ix_enable" = "1"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/mainboard/libretrend/lt1000/devicetree.cb

@@ -34,7 +34,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "1"

src/mainboard/protectli/vault_kbl/devicetree.cb

@@ -31,7 +31,6 @@ chip soc/intel/skylake
 	register "tcc_offset" = "5" # TCC of 95C
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "DspEnable" = "0"

src/mainboard/purism/librem_skl/devicetree.cb

@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "1"

src/mainboard/razer/blade_stealth_kbl/devicetree.cb

@@ -23,7 +23,6 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "ProbelessTrace" = "0"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "0"

src/soc/intel/skylake/chip.h

@@ -90,9 +90,6 @@ struct soc_intel_skylake_config {
 	/* Whether to ignore VT-d support of the SKU */
 	int ignore_vtd;
 
-	/* Probeless Trace function */
-	u8 ProbelessTrace;
-
 	/*
 	 * System Agent dynamic frequency configuration
 	 * When enabled memory will be trained at two different frequencies.

src/soc/intel/skylake/romstage/romstage.c

@@ -216,7 +216,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->MmioSize = 0x800; /* 2GB in MB */
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
-	m_cfg->ProbelessTrace = config->ProbelessTrace;
+	m_cfg->ProbelessTrace = 0;
 	m_cfg->SaGv = config->SaGv;
 	m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
 	m_cfg->RMT = config->Rmt;