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soc/intel/skylake: Drop always-zero ProbelessTrace dt setting 

This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.

Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Angel Pons 2020-12-11 17:12:32 +01:00
parent 950cdbc3e2
commit 68cf57cf33
17 changed files with 1 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/51nb/x210/devicetree.cb
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@ -32,7 +32,6 @@ chip soc/intel/skylake
register "dptf_enable" = "0"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "0"

1
src/mainboard/google/eve/devicetree.cb
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@ -35,7 +35,6 @@ chip soc/intel/skylake
register "gen3_dec" = "0x00fc0901"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
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@ -64,7 +64,6 @@ chip soc/intel/skylake
register "s0ix_enable" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/google/glados/devicetree.cb
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@ -34,7 +34,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
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@ -41,7 +41,6 @@ chip soc/intel/skylake
register "CmdTriStateDis" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -31,7 +31,6 @@ chip soc/intel/skylake
register "s0ix_enable" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -31,7 +31,6 @@ chip soc/intel/skylake
register "s0ix_enable" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "DspEnable" = "1"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -31,7 +31,6 @@ chip soc/intel/skylake
register "s0ix_enable" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
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@ -36,7 +36,6 @@ chip soc/intel/skylake
register "CmdTriStateDis" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
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@ -41,7 +41,6 @@ chip soc/intel/skylake
register "CmdTriStateDis" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -31,7 +31,6 @@ chip soc/intel/skylake
register "s0ix_enable" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/libretrend/lt1000/devicetree.cb
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@ -34,7 +34,6 @@ chip soc/intel/skylake
register "dptf_enable" = "0"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/protectli/vault_kbl/devicetree.cb
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@ -31,7 +31,6 @@ chip soc/intel/skylake
register "tcc_offset" = "5" # TCC of 95C
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "DspEnable" = "0"

1
src/mainboard/purism/librem_skl/devicetree.cb
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@ -41,7 +41,6 @@ chip soc/intel/skylake
register "dptf_enable" = "0"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -23,7 +23,6 @@ chip soc/intel/skylake
register "dptf_enable" = "0"
# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

3
src/soc/intel/skylake/chip.h
View File

@ -90,9 +90,6 @@ struct soc_intel_skylake_config {
/* Whether to ignore VT-d support of the SKU */
int ignore_vtd;
/* Probeless Trace function */
u8 ProbelessTrace;
/*
* System Agent dynamic frequency configuration
* When enabled memory will be trained at two different frequencies.

2
src/soc/intel/skylake/romstage/romstage.c
View File

@ -216,7 +216,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->MmioSize = 0x800; /* 2GB in MB */
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
m_cfg->ProbelessTrace = config->ProbelessTrace;
m_cfg->ProbelessTrace = 0;
m_cfg->SaGv = config->SaGv;
m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
m_cfg->RMT = config->Rmt;