Various fixes and improvements of the 82801xx code.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
Uwe Hermann
parent
c4590dae6a
commit
68d8a56cc5
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@ -33,21 +33,30 @@ extern void i82801xx_enable(device_t dev);
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#define RTC_CONF 0xd8
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#define GEN_PMCON_3 0xa4
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#define PCICMD 0x04
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#define PMBASE 0x40
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#define PM_BASE_ADDR 0x1100
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#define ACPI_CNTL 0x44
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#define BIOS_CNTL 0x4E
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#define GPIO_BASE 0x58
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#define GPIO_BASE_ADDR 0x1180
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#define GPIO_CNTL 0x5C
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#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
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#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */
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#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */
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#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */
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#define PIRQA_ROUT 0x60
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#define PIRQB_ROUT 0x61
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#define PIRQC_ROUT 0x62
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#define PIRQD_ROUT 0x63
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#define PIRQE_ROUT 0x68
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#define COM_DEC 0xE0
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#define LPC_EN 0xE6
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#define PIRQF_ROUT 0x69
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#define PIRQG_ROUT 0x6A
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#define PIRQH_ROUT 0x6B
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#define FUNC_DIS 0xF2
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#define CMD 0x04
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#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */
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#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */
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#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */
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#define SBUS_NUM 0x19
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#define SUB_BUS_NUM 0x1A
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#define SMLT 0x1B
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@ -32,14 +32,53 @@
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#include <arch/io.h>
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#include "i82801xx.h"
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#define PMBASE_ADDR 0x00000400 /* ACPI Base Address Register */
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#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
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#define NMI_OFF 0
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void i82801xx_enable_ioapic(struct device *dev)
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/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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* 0x02 - 0010 = Reserved
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* 0x03 - 0011 = IRQ3
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* 0x04 - 0100 = IRQ4
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* 0x05 - 0101 = IRQ5
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* 0x06 - 0110 = IRQ6
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* 0x07 - 0111 = IRQ7
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* 0x08 - 1000 = Reserved
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* 0x09 - 1001 = IRQ9
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* 0x0A - 1010 = IRQ10
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* 0x0B - 1011 = IRQ11
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* 0x0C - 1100 = IRQ12
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* 0x0D - 1101 = Reserved
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* 0x0E - 1110 = IRQ14
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* 0x0F - 1111 = IRQ15
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* PIRQ[n]_ROUT[7] - PIRQ Routing Control
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* 0x80 - The PIRQ is not routed.
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*/
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#define PIRQA 0x03
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#define PIRQB 0x05
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#define PIRQC 0x06
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#define PIRQD 0x07
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#define PIRQE 0x09
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#define PIRQF 0x0A
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#define PIRQG 0x0B
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#define PIRQH 0x0C
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void i82801xx_enable_apic(struct device *dev)
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{
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uint32_t reg32;
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volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
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volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
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/* Set ACPI base address (I/O space). */
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pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
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/* Enable ACPI I/O and power management. */
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pci_write_config8(dev, ACPI_CNTL, 0x10);
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reg32 = pci_read_config32(dev, GEN_CNTL);
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reg32 |= (3 << 7); /* Enable IOAPIC */
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reg32 |= (1 << 13); /* Coprocessor error enable */
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@ -58,8 +97,8 @@ void i82801xx_enable_ioapic(struct device *dev)
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die("APIC Error\n");
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/* TODO: From i82801ca, needed/useful on other ICH? */
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*ioapic_index = 3; // Select Boot Configuration register
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*ioapic_data = 1; // Use Processor System Bus to deliver interrupts
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*ioapic_index = 3; /* Select Boot Configuration register. */
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*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
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}
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void i82801xx_enable_serial_irqs(struct device *dev)
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@ -72,6 +111,87 @@ void i82801xx_enable_serial_irqs(struct device *dev)
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/* TODO: Explain/#define the real meaning of these magic numbers. */
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}
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static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
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{
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/* Route PIRQA - PIRQD. */
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pci_write_config8(dev, PIRQA_ROUT, PIRQA);
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pci_write_config8(dev, PIRQB_ROUT, PIRQB);
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pci_write_config8(dev, PIRQC_ROUT, PIRQC);
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pci_write_config8(dev, PIRQD_ROUT, PIRQD);
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/* Route PIRQE - PIRQH (for ICH2-ICH9). */
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if (ich_model >= 0x2440) {
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pci_write_config8(dev, PIRQE_ROUT, PIRQE);
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pci_write_config8(dev, PIRQF_ROUT, PIRQF);
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pci_write_config8(dev, PIRQG_ROUT, PIRQG);
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pci_write_config8(dev, PIRQH_ROUT, PIRQH);
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}
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}
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static void i82801xx_power_options(device_t dev)
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{
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uint8_t byte;
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int pwr_on = -1;
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int nmi_option;
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/* power after power fail */
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/* FIXME this doesn't work! */
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*/
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pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
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printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
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/* Set up NMI on errors. */
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byte = inb(0x61);
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byte &= ~(1 << 3); /* IOCHK# NMI Enable */
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byte &= ~(1 << 2); /* PCI SERR# Enable */
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outb(byte, 0x61);
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byte = inb(0x70);
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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byte &= ~(1 << 7); /* Set NMI. */
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outb(byte, 0x70);
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}
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}
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static void gpio_init(device_t dev, uint16_t ich_model)
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{
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/* Set the value for GPIO base address register and enable GPIO.
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* Note: ICH-ICH5 registers differ from ICH6-ICH9.
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*/
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if (ich_model <= 0x24D0) {
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pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
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} else if (ich_model >= 0x2640) {
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pci_write_config32(dev, GPIO_BASE_ICH6_9, (GPIO_BASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL_ICH6_9, 0x10);
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}
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}
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void i82801xx_rtc_init(struct device *dev)
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{
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uint8_t reg8;
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uint32_t reg32;
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int rtc_failed;
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~(1 << 1); /* Preserve the power fail state. */
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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}
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reg32 = pci_read_config32(dev, GEN_STS);
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rtc_failed |= reg32 & (1 << 2);
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rtc_init(rtc_failed);
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/* Enable access to the upper 128 byte bank of CMOS RAM. */
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pci_write_config8(dev, RTC_CONF, 0x04);
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}
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void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask)
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{
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uint16_t reg16;
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@ -87,56 +207,21 @@ void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask)
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pci_write_config16(dev, PCI_DMA_CFG, reg16);
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}
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/* TODO: Needs serious cleanup/comments. */
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void i82801xx_rtc_init(struct device *dev)
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static void i82801xx_lpc_decode_en(device_t dev, uint16_t ich_model)
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{
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uint8_t reg8;
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uint32_t reg32;
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int rtc_failed;
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~(1 << 1); /* preserve the power fail state */
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
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* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
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* Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
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* We also need to set the value for LPC I/F Enables Register.
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* Note: ICH-ICH5 registers differ from ICH6-ICH9.
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*/
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if (ich_model <= 0x24D0) {
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pci_write_config8(dev, COM_DEC, 0x10);
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pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F);
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} else if (ich_model >= 0x2640) {
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pci_write_config8(dev, LPC_IO_DEC, 0x10);
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pci_write_config16(dev, LPC_EN_ICH6_9, 0x300F);
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}
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reg32 = pci_read_config32(dev, GEN_STS);
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rtc_failed |= reg32 & (1 << 2);
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rtc_init(rtc_failed);
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}
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void i82801xx_1f0_misc(struct device *dev)
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{
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/* TODO: break this down into smaller functions */
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//move to acpi_enable or something
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/* Set ACPI base address to 0x1100 (I/O space) */
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pci_write_config32(dev, PMBASE, PM_BASE_ADDR | 1);
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/* Enable ACPI I/O and power management */
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pci_write_config8(dev, ACPI_CNTL, 0x10);
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/* Set GPIO base address to 0x1180 (I/O space) */
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pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDR | 1);
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/* Enable GPIO */
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pci_write_config8(dev, GPIO_CNTL, 0x10);
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//get rid of?
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/* Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 */
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pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
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/* Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted */
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pci_write_config8(dev, PIRQE_ROUT, 0x07);
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//move to i82801xx_init
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/* Prevent LPC disabling, enable parity errors, and SERR# (System Error) */
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pci_write_config16(dev, PCI_COMMAND, 0x014f);
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/* Enable access to the upper 128 byte bank of CMOS RAM */
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pci_write_config8(dev, RTC_CONF, 0x04);
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/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB */
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pci_write_config8(dev, COM_DEC, 0x10);
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/* LPT decode defaults to 0x378-0x37F and 0x778-0x77F
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* Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 */
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/* Enable: COMA, COMB, LPT, Floppy
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* Disable: Microcontroller, Sound, Gameport */
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pci_write_config16(dev, LPC_EN, 0x000F);
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}
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static void enable_hpet(struct device *dev)
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@ -146,7 +231,7 @@ static void enable_hpet(struct device *dev)
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uint32_t code = (0 & 0x3);
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reg32 = pci_read_config32(dev, GEN_CNTL);
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reg32 |= (1 << 17); /* Enable HPET */
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reg32 |= (1 << 17); /* Enable HPET. */
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/*
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* Bits [16:15] Memory Address Range
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* 00 FED0_0000h - FED0_03FFh
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@ -156,67 +241,45 @@ static void enable_hpet(struct device *dev)
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*/
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reg32 &= ~(3 << 15); /* Clear it */
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reg32 |= (code << 15);
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/* reg32 is never written to anywhere? */
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/* TODO: reg32 is never written to anywhere? */
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printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
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#endif
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}
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static void lpc_init(struct device *dev)
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{
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uint8_t byte;
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int pwr_on = -1;
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int nmi_option;
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uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
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/* IO APIC initialization */
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i82801xx_enable_ioapic(dev);
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/* Set the value for PCI command register. */
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pci_write_config16(dev, PCI_COMMAND, 0x000f);
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/* IO APIC initialization. */
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i82801xx_enable_apic(dev);
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i82801xx_enable_serial_irqs(dev);
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/* TODO: Find out if this is being used/works */
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#ifdef SUSPICIOUS_LOOKING_CODE
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/* The ICH-4 datasheet does not mention this configuration register.
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* This code may have been inherited (incorrectly) from code for
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* the AMD 766 southbridge, which *does* support this functionality.
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*/
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/* Setup the PIRQ. */
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i82801xx_pirq_init(dev, ich_model);
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/* Posted memory write enable */
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byte = pci_read_config8(dev, 0x46);
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pci_write_config8(dev, 0x46, byte | (1 << 0));
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#endif
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/* Setup power options. */
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i82801xx_power_options(dev);
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/* power after power fail */
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/* FIXME this doesn't work! */
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*/
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pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
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printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
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/* Set the state of the GPIO lines. */
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gpio_init(dev, ich_model);
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/* Set up NMI on errors */
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byte = inb(0x61);
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byte &= ~(1 << 3); /* IOCHK# NMI Enable */
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byte &= ~(1 << 2); /* PCI SERR# Enable */
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outb(byte, 0x61);
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byte = inb(0x70);
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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byte &= ~(1 << 7); /* Set NMI */
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outb(byte, 0x70);
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}
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/* Initialize the real time clock */
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/* Initialize the real time clock. */
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i82801xx_rtc_init(dev);
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/* Route DMA. */
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i82801xx_lpc_route_dma(dev, 0xff);
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/* Initialize isa dma */
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/* Initialize ISA DMA. */
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isa_dma_init();
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i82801xx_1f0_misc(dev);
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/* Initialize the High Precision Event Timers, if present */
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/* Setup decode ports and LPC I/F enables. */
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i82801xx_lpc_decode_en(dev, ich_model);
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/* Initialize the High Precision Event Timers, if present. */
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enable_hpet(dev);
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}
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@ -224,10 +287,10 @@ static void i82801xx_lpc_read_resources(device_t dev)
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{
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struct resource *res;
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/* Get the normal pci resources of this device */
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add an extra subtractive resource for both memory and I/O */
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/* Add an extra subtractive resource for both memory and I/O. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->flags =
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IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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