src: Move 'static' to the beginning of declaration
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -212,7 +212,7 @@
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*/
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#define GEC_CONFIG 0
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const static CODECENTRY gizmo_codec_alc272[] =
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static const CODECENTRY gizmo_codec_alc272[] =
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{
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/* NID, PinConfig */
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{0x11, 0x411111F0}, /* S/PDIF-OUT2 unused */
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@ -88,7 +88,7 @@ static void set_db(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
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}
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}
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const static u8 max_tap[3] = {12, 10, 13};
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static const u8 max_tap[3] = {12, 10, 13};
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static int increment_dq_dqs(const struct sysinfo *s,
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struct dll_setting *dq_dqs_setting)
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@ -540,7 +540,7 @@ static void set_rank_write_level(struct sysinfo *s, u8 channel, u8 config,
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u32 emrs1;
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/* Is shifted by bits 2 later so u8 can be used to reduce size */
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const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */
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static const u8 emrs1_lut[8][4][4] = { /* [Config][Leveling Rank][Rank] */
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{ /* Config 0: 2R2R */
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{0x11, 0x00, 0x91, 0x00},
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{0x00, 0x11, 0x91, 0x00},
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@ -437,7 +437,7 @@ static void program_timings(struct sysinfo *s)
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5200
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};
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const static u8 ddr3_turnaround_tab[3][6][4] = {
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static const u8 ddr3_turnaround_tab[3][6][4] = {
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{ /* DDR3 800 */
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{0x9, 0x7, 0x7, 0x9}, /* CL = 5 */
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{0x9, 0x7, 0x8, 0x8}, /* CL = 6 */
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@ -459,7 +459,7 @@ static void program_timings(struct sysinfo *s)
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};
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/* [DDR freq][0x26F & 1][pagemod] */
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const static u8 ddr2_x252_tab[2][2][2] = {
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static const u8 ddr2_x252_tab[2][2][2] = {
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{ /* DDR2 667 */
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{12, 16},
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{14, 18}
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@ -470,7 +470,7 @@ static void program_timings(struct sysinfo *s)
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}
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};
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const static u8 ddr3_x252_tab[3][2][2] = {
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static const u8 ddr3_x252_tab[3][2][2] = {
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{ /* DDR3 800 */
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{16, 20},
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{18, 22}
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@ -133,7 +133,7 @@ static const uint8_t rec_hash_data[REC_HASH_NV_SIZE] = { };
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* i.e. those which should not be possible to delete or modify once
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* the RO exits, and the rest of the NVRAM spaces.
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*/
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const static TPMA_NV ro_space_attributes = {
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static const TPMA_NV ro_space_attributes = {
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.TPMA_NV_PPWRITE = 1,
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.TPMA_NV_AUTHREAD = 1,
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.TPMA_NV_PPREAD = 1,
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@ -142,7 +142,7 @@ const static TPMA_NV ro_space_attributes = {
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.TPMA_NV_POLICY_DELETE = 1,
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};
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const static TPMA_NV rw_space_attributes = {
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static const TPMA_NV rw_space_attributes = {
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.TPMA_NV_PPWRITE = 1,
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.TPMA_NV_AUTHREAD = 1,
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.TPMA_NV_PPREAD = 1,
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@ -153,7 +153,7 @@ const static TPMA_NV rw_space_attributes = {
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* This policy digest was obtained using TPM2_PolicyPCR
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* selecting only PCR_0 with a value of all zeros.
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*/
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const static uint8_t pcr0_unchanged_policy[] = {
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static const uint8_t pcr0_unchanged_policy[] = {
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0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D,
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0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79,
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0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1};
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@ -29,7 +29,7 @@ static int create_tcpa_metadata(const struct region_device *rdev,
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{
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int i;
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struct region_device fmap;
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const static char *fmap_cbfs_names[] = {
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static const char *fmap_cbfs_names[] = {
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"COREBOOT",
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"FW_MAIN_A",
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"FW_MAIN_B",
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@ -43,7 +43,7 @@
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* waiting for each device to become available, a single delay will be
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* executed.
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*/
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const static struct stoneyridge_aoac aoac_devs[] = {
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static const struct stoneyridge_aoac aoac_devs[] = {
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{ (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),
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(FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) },
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{ FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA },
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@ -115,7 +115,7 @@ void SetFchMidParams(FCH_INTERFACE *params)
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* amd_pci_int_defs.h, just add the pair at the end of this table.
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* Order is not important.
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*/
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const static struct irq_idx_name irq_association[] = {
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static const struct irq_idx_name irq_association[] = {
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{ PIRQ_A, "INTA#" },
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{ PIRQ_B, "INTB#" },
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{ PIRQ_C, "INTC#" },
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