remove more warnings, and fix some boards (watchdog.h)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/dell/s1850/mptable.c

@@ -4,7 +4,7 @@
 #include <string.h>
 #include <stdint.h>
 
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
 {
 	static const char sig[4] = "PCMP";
 	static const char oem[8] = "DELL    ";

src/mainboard/dell/s1850/romstage.c

@@ -19,7 +19,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "debug.c"
 #include "watchdog.c"
-#include "reset.c"
+// Remove comment if resets in this file are actually used.
+// #include "reset.c"
 #include "s1850_fixups.c"
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"

src/mainboard/supermicro/x6dhe_g2/Kconfig

@@ -12,6 +12,7 @@ config BOARD_SUPERMICRO_X6DHE_G2
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_1024
+	select USE_WATCHDOG_ON_BOOT
 	select DRIVERS_GENERIC_DEBUG
 
 config MAINBOARD_DIR

src/mainboard/supermicro/x6dhr_ig/Kconfig

@@ -11,6 +11,7 @@ config BOARD_SUPERMICRO_X6DHR_IG
 	select BOARD_HAS_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
+	select USE_WATCHDOG_ON_BOOT
 	select BOARD_ROMSIZE_KB_1024
 
 config MAINBOARD_DIR

src/mainboard/supermicro/x6dhr_ig2/Kconfig

@@ -11,6 +11,7 @@ config BOARD_SUPERMICRO_X6DHR_IG2
 	select BOARD_HAS_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
+	select USE_WATCHDOG_ON_BOOT
 	select BOARD_ROMSIZE_KB_1024
 
 config MAINBOARD_DIR

src/mainboard/tyan/s2735/Kconfig

@@ -13,6 +13,7 @@ config BOARD_TYAN_S2735
 	select UDELAY_TSC
 	select HAVE_OPTION_TABLE
 	select USE_DCACHE_RAM
+	select USE_WATCHDOG_ON_BOOT
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR

src/southbridge/intel/i82801ex/i82801ex_lpc.c

@@ -232,7 +232,7 @@ const unsigned long hpet_address = 0xfed0000;
 	dword &= ~(3 << 15); /* clear it */
 	dword |= (code<<15);
 
-	printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) );
+	printk_debug("enabling HPET @0x%lx\n", hpet_address | (code <<12) );
 }
 
 static void lpc_init(struct device *dev)

src/southbridge/intel/i82801ex/i82801ex_pci.c

@@ -7,7 +7,6 @@
 
 static void pci_init(struct device *dev)
 {
-	uint32_t dword;
 	uint16_t word;
 
 	/* Clear system errors */
@@ -17,6 +16,7 @@ static void pci_init(struct device *dev)
 
 #if 0
 	/* System error enable */
+	uint32_t dword;
 	dword = pci_read_config32(dev, 0x04);
 	dword |= (1<<8); /* SERR# Enable */
 	dword |= (1<<6); /* Parity Error Response */

src/southbridge/intel/i82801ex/i82801ex_sata.c

@@ -7,10 +7,7 @@
 
 static void sata_init(struct device *dev)
 {
-
-	uint16_t word;
-
-  printk_debug("SATA init\n");
+  	printk_debug("SATA init\n");
 	/* SATA configuration */
 	pci_write_config8(dev, 0x04, 0x07);
 	pci_write_config8(dev, 0x09, 0x8f);

src/southbridge/intel/i82801ex/i82801ex_smbus.c

@@ -8,24 +8,28 @@
 #include "i82801ex.h"
 #include "i82801ex_smbus.h"
 
-static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
+static int lsmbus_read_byte(device_t dev, u8 address)
 {
-	unsigned device;
+	u16 device;
 	struct resource *res;
+	struct bus *pbus;
 
 	device = dev->path.i2c.device;
-	res = find_resource(bus->dev, 0x20);
-	
+	pbus = get_pbus_smbus(dev);
+	res = find_resource(pbus->dev, 0x20);
+
 	return do_smbus_read_byte(res->base, device, address);
 }
 
 static struct smbus_bus_operations lops_smbus_bus = {
 	.read_byte  = lsmbus_read_byte,
 };
+
 static struct pci_operations lops_pci = {
 	/* The subsystem id follows the ide controller */
 	.set_subsystem = 0,
 };
+
 static struct device_operations smbus_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,

src/southbridge/intel/i82801ex/i82801ex_smbus.h

@@ -46,7 +46,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 	return loops?0:-1;
 }
 
-static int smbus_wait_until_blk_done(unsigned smbus_io_base)
+static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
 {
 	unsigned loops = SMBUS_TIMEOUT;
 	unsigned char byte;

src/southbridge/intel/pxhd/pxhd_bridge.c

@@ -64,15 +64,15 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
 }
 static void pcix_init(device_t dev)
 {
-	uint32_t dword;
-	uint16_t word;
-	uint8_t byte;
-	int nmi_option;
-
 	/* Bridge control ISA enable */
 	pci_write_config8(dev, 0x3e, 0x07);
 
+#warning "Please review lots of dead code here."
 #if 0
+	int nmi_option;
+	uint32_t dword;
+	uint16_t word;
+	uint8_t byte;
 
 	/* Enable memory write and invalidate ??? */
 	byte = pci_read_config8(dev, 0x04);