Revert "model_206ax: Use parallel MP init"
This reverts commit 5fbe788bae
.
This commit was submitted without its parent being submitted,
resulting in coreboot not building.
Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
parent
5fbe788bae
commit
68f688896c
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@ -102,6 +102,7 @@ void intel_model_206ax_finalize_smm(void);
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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void smm_relocate(void);
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#endif
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#endif
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@ -91,6 +91,7 @@ void intel_model_2065x_finalize_smm(void);
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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void smm_relocate(void);
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#endif
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#endif
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@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS
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select TSC_SYNC_MFENCE
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select CPU_INTEL_COMMON
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select PARALLEL_MP
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config BOOTBLOCK_CPU_INIT
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string
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@ -121,6 +121,7 @@ void intel_model_206ax_finalize_smm(void);
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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void smm_relocate(void);
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#endif
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#endif
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@ -15,7 +15,6 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <string.h>
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@ -24,7 +23,6 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/intel/speedstep.h>
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#include <cpu/intel/turbo.h>
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@ -423,6 +421,83 @@ static void configure_mca(void)
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wrmsr(IA32_MC0_STATUS + (i * 4), msr);
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}
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int cpu_get_apic_id_map(int *apic_id_map)
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{
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struct cpuid_result result;
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unsigned int threads_per_package, threads_per_core, i, shift = 0;
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/* Logical processors (threads) per core */
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result = cpuid_ext(0xb, 0);
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threads_per_core = result.ebx & 0xffff;
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/* Logical processors (threads) per package */
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result = cpuid_ext(0xb, 1);
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threads_per_package = result.ebx & 0xffff;
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if (threads_per_core == 1)
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shift++;
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for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; i++)
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apic_id_map[i] = i << shift;
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return threads_per_package;
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}
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/*
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* Initialize any extra cores/threads in this package.
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*/
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static void intel_cores_init(struct device *cpu)
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{
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struct cpuid_result result;
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unsigned int threads_per_package, threads_per_core, i;
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/* Logical processors (threads) per core */
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result = cpuid_ext(0xb, 0);
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threads_per_core = result.ebx & 0xffff;
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/* Logical processors (threads) per package */
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result = cpuid_ext(0xb, 1);
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threads_per_package = result.ebx & 0xffff;
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/* Only initialize extra cores from BSP */
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if (cpu->path.apic.apic_id)
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return;
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printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n",
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cpu->path.apic.apic_id, threads_per_package/threads_per_core,
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threads_per_core);
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for (i = 1; i < threads_per_package; ++i) {
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struct device_path cpu_path;
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struct device *new;
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/* Build the CPU device path */
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cpu_path.type = DEVICE_PATH_APIC;
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cpu_path.apic.apic_id =
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cpu->path.apic.apic_id + i;
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/* Update APIC ID if no hyperthreading */
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if (threads_per_core == 1)
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cpu_path.apic.apic_id <<= 1;
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/* Allocate the new CPU device structure */
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new = alloc_dev(cpu->bus, &cpu_path);
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if (!new)
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continue;
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printk(BIOS_DEBUG, "CPU: %u has core %u\n",
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cpu->path.apic.apic_id,
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new->path.apic.apic_id);
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/* Start the new CPU */
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if (is_smp_boot() && !start_cpu(new)) {
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/* Record the error in cpu? */
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printk(BIOS_ERR, "CPU %u would not start!\n",
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new->path.apic.apic_id);
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}
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}
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}
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static void model_206ax_init(struct device *cpu)
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{
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char processor_name[49];
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@ -430,6 +505,8 @@ static void model_206ax_init(struct device *cpu)
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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intel_update_microcode_from_cbfs();
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/* Clear out pending MCEs */
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configure_mca();
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@ -437,6 +514,10 @@ static void model_206ax_init(struct device *cpu)
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fill_processor_name(processor_name);
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printk(BIOS_INFO, "CPU: %s.\n", processor_name);
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/* Setup MTRRs based on physical address size */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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/* Setup Page Attribute Tables (PAT) */
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// TODO set up PAT
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@ -467,81 +548,9 @@ static void model_206ax_init(struct device *cpu)
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/* Enable Turbo */
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enable_turbo();
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}
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/* MP initialization support. */
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static const void *microcode_patch;
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static void pre_mp_init(void)
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{
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/* Setup MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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}
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static int get_cpu_count(void)
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{
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struct cpuid_result result;
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unsigned int threads_per_package, threads_per_core;
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/* Logical processors (threads) per core */
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result = cpuid_ext(0xb, 0);
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threads_per_core = result.ebx & 0xffff;
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ASSERT(threads_per_core != 0);
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/* Logical processors (threads) per package */
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result = cpuid_ext(0xb, 1);
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threads_per_package = result.ebx & 0xffff;
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printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
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threads_per_package / threads_per_core, threads_per_package);
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return threads_per_package;
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}
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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microcode_patch = intel_microcode_find();
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*microcode = microcode_patch;
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*parallel = 1;
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}
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static void per_cpu_smm_trigger(void)
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{
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/* Relocate the SMM handler. */
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smm_relocate();
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/* After SMM relocation a 2nd microcode load is required. */
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intel_microcode_load_unlocked(microcode_patch);
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}
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static void post_mp_init(void)
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{
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/* Now that all APs have been relocated as well as the BSP let SMIs
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* start flowing. */
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southbridge_smm_init();
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = smm_info,
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.get_microcode_info = get_microcode_info,
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.pre_mp_smm_init = smm_initialize,
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.per_cpu_smm_trigger = per_cpu_smm_trigger,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = post_mp_init,
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};
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void bsp_init_and_start_aps(struct bus *cpu_bus)
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{
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if (mp_init_with_smm(cpu_bus, &mp_ops))
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printk(BIOS_ERR, "MP initialization failure.\n");
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/* Start up extra cores */
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intel_cores_init(cpu);
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}
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static struct device_operations cpu_dev_ops = {
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@ -11,10 +11,6 @@
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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void bsp_init_and_start_aps(struct bus *cpu_bus);
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/* These helpers are for performing SMM relocation. */
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void southbridge_smm_init(void);
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void southbridge_trigger_smi(void);
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@ -22,10 +18,3 @@ void southbridge_clear_smi_status(void);
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u32 northbridge_get_tseg_base(void);
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int cpu_get_apic_id_map(int *apic_id_map);
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void northbridge_write_smram(u8 smram);
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void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size);
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void smm_initialize(void);
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void southbridge_smm_clear_state(void);
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void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase);
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void smm_relocate(void);
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@ -23,12 +23,10 @@
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#include <device/pci.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <console/console.h>
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#include <smp/node.h>
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#include "smi.h"
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#define SMRR_SUPPORTED (1 << 11)
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@ -294,78 +292,3 @@ void smm_lock(void)
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northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG);
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}
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void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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{
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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fill_in_relocation_params(&smm_reloc_params);
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setup_ied_area(&smm_reloc_params);
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*perm_smbase = smm_reloc_params.smram_base;
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*perm_smsize = smm_reloc_params.smram_size;
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*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
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}
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void smm_initialize(void)
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{
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/* Clear the SMM state in the southbridge. */
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southbridge_smm_clear_state();
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/*
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* Run the relocation handler for on the BSP to check and set up
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* parallel SMM relocation.
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*/
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smm_initiate_relocation();
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}
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/* The relocation work is actually performed in SMM context, but the code
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* resides in the ramstage module. This occurs by trampolining from the default
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* SMRAM entry point to here. */
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void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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{
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msr_t mtrr_cap;
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struct smm_relocation_params *relo_params = &smm_reloc_params;
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em64t101_smm_state_save_area_t *save_state;
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u32 smbase = staggered_smbase;
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u32 iedbase = relo_params->ied_base;
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printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
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/* Make appropriate changes to the save state map. */
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printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
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smbase, iedbase);
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save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
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sizeof(*save_state));
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save_state->smbase = smbase;
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save_state->iedbase = iedbase;
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/* Write EMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRR_CAP_MSR);
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if (mtrr_cap.lo & SMRR_SUPPORTED && !IS_ENABLED(CONFIG_HAS_NO_SMRR))
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write_smrr(relo_params);
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}
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/*
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* The default SMM entry can happen in parallel or serially. If the
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* default SMM entry is done in parallel the BSP has already setup
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* the saving state to each CPU's MSRs. At least one save state size
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* is required for the initial SMM entry for the BSP to determine if
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* parallel SMM relocation is even feasible.
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*/
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void smm_relocate(void)
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{
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/*
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* If smm_save_state_in_msrs is non-zero then parallel SMM relocation
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* shall take place. Run the relocation handler a second time on the
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* BSP to do * the final move. For APs, a relocation handler always
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* needs to be run.
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*/
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if (!boot_cpu())
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smm_initiate_relocation();
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}
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@ -525,7 +525,7 @@ static const struct pci_driver mc_driver_158 __pci_driver = {
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static void cpu_bus_init(device_t dev)
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{
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bsp_init_and_start_aps(dev->link_list);
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initialize_cpus(dev->link_list);
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}
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static struct device_operations cpu_bus_ops = {
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@ -22,7 +22,7 @@
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#include <stdint.h>
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#include <string.h>
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#include <elog.h>
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#include <southbridge/intel/common/pmutils.h>
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#include "pch.h"
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void pch_log_state(void)
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{
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@ -68,6 +68,9 @@ int pch_silicon_revision(void);
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int pch_silicon_type(void);
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int pch_silicon_supported(int type, int rev);
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
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#if IS_ENABLED(CONFIG_ELOG)
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void pch_log_state(void);
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#endif
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#else /* __PRE_RAM__ */
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void enable_smbus(void);
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void enable_usb_bar(void);
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@ -123,6 +123,5 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done);
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void southbridge_finalize_all(void);
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void southbridge_smi_monitor(void);
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em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd);
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void pch_log_state(void);
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#endif /*INTEL_COMMON_PMUTIL_H */
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@ -159,29 +159,3 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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"d" (APM_CNT)
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);
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}
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void southbridge_smm_clear_state(void)
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{
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u32 smi_en;
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if (IS_ENABLED(CONFIG_ELOG))
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/* Log events from chipset before clearing */
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pch_log_state();
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
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smi_en = inl(get_pmbase() + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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printk(BIOS_DEBUG, "\n");
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/* Dump and clear status registers */
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reset_smi_status();
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reset_pm1_status();
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reset_tco_status();
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reset_gpe0_status();
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}
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