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mb/siemens/mc_ehl2: Disable L1 prefetcher 

As for mainboard mc_ehl1, a hard real-time dependency is also required
for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive
which in the end leads to an increased number of cache misses. Disabling
the L1 prefetcher boosts up the performance (in some cases by more than
10 %) in this specific use case.

Change-Id: I07b27dd672533e693a6c2987d16f54333850760e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2022-11-24 08:38:19 +01:00 committed by Felix Held
parent 3627f2903c
commit 68fb5437f9
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
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@ -135,6 +135,9 @@ chip soc/intel/elkhartlake
.vcc_low_high_us = 50, .vcc_low_high_us = 50,
}" }"
# Disable L1 prefetcher for real-time demands
register "L1_prefetcher_disable" = "true"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device