veyron: Add veyron_rialto board

Derived from of veyron_brain with new memory configuration.

BUG=chrome-os-partner:35072
TEST=built and boot on rialto-rev0 boards.
BRANCH=veyron

Change-Id: I2c6f74d231e39de76ef2399fdb20efae977b34fa
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 17d66e5f58562427badd6973ebb053f58573c040
Original-Change-Id: I8626ff5da8098ca120481b8cda0c6703f806711e
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238946
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Trybot-Ready: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/mainboard/google/Kconfig

@@ -73,6 +73,8 @@ config BOARD_GOOGLE_VEYRON_MIGHTY
 	bool "Veyron_Mighty"
 config BOARD_GOOGLE_VEYRON_PINKY
 	bool "Veyron_Pinky"
+config BOARD_GOOGLE_VEYRON_RIALTO
+        bool "Veyron_Rialto"
 config BOARD_GOOGLE_VEYRON_SPEEDY
 	bool "Veyron_Speedy"
 endchoice
@@ -103,6 +105,7 @@ source "src/mainboard/google/veyron_danger/Kconfig"
 source "src/mainboard/google/veyron_jerry/Kconfig"
 source "src/mainboard/google/veyron_mighty/Kconfig"
 source "src/mainboard/google/veyron_pinky/Kconfig"
+source "src/mainboard/google/veyron_rialto/Kconfig"
 source "src/mainboard/google/veyron_speedy/Kconfig"
 
 config MAINBOARD_VENDOR

src/mainboard/google/veyron_rialto/Kconfig

@@ -0,0 +1,89 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_GOOGLE_VEYRON_RIALTO
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select BOARD_ID_SUPPORT
+	select BOARD_ROMSIZE_KB_4096
+	select CHROMEOS_VBNV_FLASH
+	select COMMON_CBFS_SPI_WRAPPER
+	select HAVE_HARD_RESET
+	select MAINBOARD_DO_NATIVE_VGA_INIT
+	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_BOOTBLOCK_INIT
+	select RAM_CODE_SUPPORT
+	select RETURN_FROM_VERSTAGE
+	select SOC_ROCKCHIP_RK3288
+	select SPI_FLASH
+	select SPI_FLASH_GIGADEVICE
+	select SPI_FLASH_WINBOND
+	select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+	string
+	default google/veyron_rialto
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Veyron_Rialto"
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config VBOOT_RAMSTAGE_INDEX
+	hex
+	default 0x3
+
+config BOOT_MEDIA_SPI_BUS
+        int
+        default 2
+
+config DRAM_SIZE_MB
+	int
+	default 1024
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x20
+
+config CONSOLE_SERIAL_UART_ADDRESS
+	hex
+	depends on CONSOLE_SERIAL_UART
+	default 0xFF690000
+
+# FIXME(dhendrix): This is a gross hack intended to get us past
+# display init which currently hangs the machine. It will be removed
+# once we've re-factored the display init code to properly handle
+# various types of displays.
+config SKIP_DISPLAY_INIT_HACK
+	int
+	default 1
+
+config PMIC_BUS
+	int
+	default 0
+
+endif #  BOARD_GOOGLE_VEYRON_RIALTO

src/mainboard/google/veyron_rialto/Makefile.inc

@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+bootblock-y += bootblock.c
+bootblock-y += boardid.c
+bootblock-y += chromeos.c
+bootblock-y += reset.c
+
+verstage-y += boardid.c
+verstage-y += chromeos.c
+verstage-y += reset.c
+
+romstage-y += boardid.c
+romstage-y += romstage.c
+romstage-y += sdram_configs.c
+romstage-y += reset.c
+
+ramstage-y += boardid.c
+ramstage-y += chromeos.c
+ramstage-y += mainboard.c
+ramstage-y += reset.c
+
+bootblock-y += memlayout.ld
+verstage-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld

src/mainboard/google/veyron_rialto/board.h

@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H
+#define __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H
+
+#include <boardid.h>
+#include <gpio.h>
+
+#define GPIO_RESET	GPIO(0, B, 5)
+
+/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */
+
+#endif	/* __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H */

src/mainboard/google/veyron_rialto/boardid.c

@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <stdlib.h>
+
+uint8_t board_id(void)
+{
+	static int id = -1;
+	static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
+		[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
+
+	if (id < 0) {
+		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
+		printk(BIOS_SPEW, "Board ID: %d.\n", id);
+	}
+
+	return id;
+}
+
+uint32_t ram_code(void)
+{
+	uint32_t code;
+	static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
+		[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
+
+	code = gpio_base2_value(pins, ARRAY_SIZE(pins));
+	printk(BIOS_SPEW, "RAM Config: %u.\n", code);
+
+	return code;
+}

src/mainboard/google/veyron_rialto/bootblock.c

@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <delay.h>
+#include <reset.h>
+#include <soc/clock.h>
+#include <soc/i2c.h>
+#include <soc/grf.h>
+#include <soc/pmu.h>
+#include <soc/rk808.h>
+#include <soc/spi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+void bootblock_mainboard_early_init()
+{
+	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) {
+		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
+		writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+	}
+
+}
+
+void bootblock_mainboard_init(void)
+{
+	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
+	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
+	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
+	assert(CONFIG_PMIC_BUS == 0);	/* must correspond with IOMUX */
+	i2c_init(CONFIG_PMIC_BUS, 400*KHz);
+
+	/* Slowly raise to max CPU voltage to prevent overshoot */
+	rk808_configure_buck(1, 1200);
+	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
+	rk808_configure_buck(1, 1400);
+	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
+	rkclk_configure_cpu();
+
+	if (rkclk_was_watchdog_reset()) {
+		printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+		hard_reset();
+	}
+
+	/* i2c1 for tpm */
+	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+	i2c_init(1, 400*KHz);
+
+	/* spi2 for firmware ROM */
+	writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
+	writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
+
+	setup_chromeos_gpios();
+}

src/mainboard/google/veyron_rialto/chromeos.c

@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+#define GPIO_WP		GPIO(7, A, 6)
+#define GPIO_POWER	GPIO(0, A, 5)
+#define GPIO_RECOVERY	GPIO(0, B, 1)
+
+void setup_chromeos_gpios(void)
+{
+	gpio_input(GPIO_WP);
+	gpio_input(GPIO_POWER);
+	gpio_input_pullup(GPIO_RECOVERY);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	int count = 0;
+
+	/* Write Protect: active low */
+	gpios->gpios[count].port = GPIO_WP.raw;
+	gpios->gpios[count].polarity = ACTIVE_LOW;
+	gpios->gpios[count].value = gpio_get(GPIO_WP);
+	strncpy((char *)gpios->gpios[count].name, "write protect",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Recovery: active low */
+	gpios->gpios[count].port = GPIO_RECOVERY.raw;
+	gpios->gpios[count].polarity = ACTIVE_LOW;
+	gpios->gpios[count].value = gpio_get(GPIO_RECOVERY);
+	strncpy((char *)gpios->gpios[count].name, "recovery",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Power Button: GPIO active low */
+	gpios->gpios[count].port = GPIO_POWER.raw;
+	gpios->gpios[count].polarity = ACTIVE_LOW;
+	gpios->gpios[count].value = -1;
+	strncpy((char *)gpios->gpios[count].name, "power",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Developer: GPIO active high */
+	gpios->gpios[count].port = -1;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = get_developer_mode_switch();
+	strncpy((char *)gpios->gpios[count].name, "developer",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Reset: GPIO active high (output) */
+	gpios->gpios[count].port = GPIO_RESET.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = -1;
+	strncpy((char *)gpios->gpios[count].name, "reset",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+	gpios->count = count;
+
+	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return !gpio_get(GPIO_RECOVERY);
+}
+
+int get_write_protect_state(void)
+{
+	return !gpio_get(GPIO_WP);
+}
+

src/mainboard/google/veyron_rialto/devicetree.cb

@@ -0,0 +1,25 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# TODO fill with Versatile Express board data in QEMU.
+chip soc/rockchip/rk3288
+	device cpu_cluster 0 on end
+	register "vop_id" = "1"
+	register "framebuffer_bits_per_pixel" = "16"
+end

src/mainboard/google/veyron_rialto/mainboard.c

@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/i2c.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/display.h>
+#include <soc/grf.h>
+#include <soc/soc.h>
+#include <soc/pmu.h>
+#include <soc/clock.h>
+#include <soc/rk808.h>
+#include <soc/spi.h>
+#include <soc/i2c.h>
+#include <symbols.h>
+#include <vbe.h>
+
+#include "board.h"
+
+static void configure_usb(void)
+{
+	gpio_output(GPIO(0, B, 3), 1);			/* HOST1_PWR_EN */
+	gpio_output(GPIO(0, B, 4), 1);			/* USBOTG_PWREN_H */
+	gpio_output(GPIO(7, C, 5), 1);			/* 5V_DRV */
+}
+
+static void configure_emmc(void)
+{
+	writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
+	writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
+	writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+
+	gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
+}
+
+static void configure_codec(void)
+{
+	writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);	/* CODEC I2C */
+	i2c_init(2, 400*KHz);				/* CODEC I2C */
+
+	writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
+	writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+
+	rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
+
+	/* AUDIO IO domain 1.8V voltage selection */
+	writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+	rkclk_configure_i2s(12288000);
+}
+
+static void mainboard_init(device_t dev)
+{
+	gpio_output(GPIO_RESET, 0);
+
+	configure_usb();
+	configure_emmc();
+	configure_codec();
+	/* No video. */
+}
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
+
+void lb_board(struct lb_header *header)
+{
+	struct lb_range *dma;
+
+	dma = (struct lb_range *)lb_new_record(header);
+	dma->tag = LB_TAB_DMA;
+	dma->size = sizeof(*dma);
+	dma->range_start = (uintptr_t)_dma_coherent;
+	dma->range_size = _dma_coherent_size;
+}
+
+void mainboard_power_on_backlight(void)
+{
+}

src/mainboard/google/veyron_rialto/memlayout.ld

@@ -0,0 +1 @@
+#include <soc/memlayout.ld>

src/mainboard/google/veyron_rialto/reset.c

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <gpio.h>
+#include <reset.h>
+
+#include "board.h"
+
+void hard_reset(void)
+{
+	gpio_output(GPIO_RESET, 1);
+	while (1)
+		;
+}

src/mainboard/google/veyron_rialto/romstage.c

@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <arch/exception.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <armv7.h>
+#include <assert.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <delay.h>
+#include <program_loading.h>
+#include <soc/sdram.h>
+#include <soc/clock.h>
+#include <soc/pwm.h>
+#include <soc/grf.h>
+#include <soc/rk808.h>
+#include <soc/tsadc.h>
+#include <stdlib.h>
+#include <symbols.h>
+#include <timestamp.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+static void regulate_vdd_log(unsigned int mv)
+{
+	unsigned int duty_ns;
+	const u32 period_ns = 2000;	/* pwm period: 2000ns */
+	const u32 max_regulator_mv = 1350;	/* 1.35V */
+	const u32 min_regulator_mv = 870;	/* 0.87V */
+
+	writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+
+	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
+
+	duty_ns = (max_regulator_mv - mv) * period_ns /
+			(max_regulator_mv - min_regulator_mv);
+
+	pwm_init(1, period_ns, duty_ns);
+}
+
+static void configure_l2ctlr(void)
+{
+	uint32_t l2ctlr;
+
+	l2ctlr = read_l2ctlr();
+	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+	/*
+	* Data RAM write latency: 2 cycles
+	* Data RAM read latency: 2 cycles
+	* Data RAM setup latency: 1 cycle
+	* Tag RAM write latency: 1 cycle
+	* Tag RAM read latency: 1 cycle
+	* Tag RAM setup latency: 1 cycle
+	*/
+	l2ctlr |= (1 << 3 | 1 << 0);
+	write_l2ctlr(l2ctlr);
+}
+
+static void sdmmc_power_off(void)
+{
+	rk808_configure_ldo(4, 0); /* VCCIO_SD */
+	rk808_configure_ldo(5, 0); /* VCC33_SD */
+}
+
+void main(void)
+{
+#if CONFIG_COLLECT_TIMESTAMPS
+	uint64_t start_romstage_time;
+	uint64_t before_dram_time;
+	uint64_t after_dram_time;
+	uint64_t base_time = timestamp_get();
+	start_romstage_time = timestamp_get();
+#endif
+
+	console_init();
+	configure_l2ctlr();
+	tsadc_init();
+
+	/* Need to power cycle SD card to ensure it is properly reset. */
+	sdmmc_power_off();
+
+	/* vdd_log 1200mv is enough for ddr run 666Mhz */
+	regulate_vdd_log(1200);
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = timestamp_get();
+#endif
+	sdram_init(get_sdram_config());
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = timestamp_get();
+#endif
+
+	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
+	mmu_config_range((uintptr_t)_dram/MiB,
+			 CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK);
+	mmu_config_range((uintptr_t)_dma_coherent/MiB,
+			 _dma_coherent_size/MiB, DCACHE_OFF);
+
+	cbmem_initialize_empty();
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time);
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+
+#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
+	void *entry = vboot2_load_ramstage();
+	if (entry != NULL)
+		stage_exit(entry);
+#endif
+
+	run_ramstage();
+}

src/mainboard/google/veyron_rialto/sdram_configs.c

@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <arch/io.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <soc/sdram.h>
+#include <string.h>
+#include <types.h>
+
+static struct rk3288_sdram_params sdram_configs[] = {
+#include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc"	/* ram_code = 0000 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0001 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0100 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0101 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0110 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0111 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1000 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1001 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1010 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1011 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1101 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1110 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1111 */
+};
+
+const struct rk3288_sdram_params *get_sdram_config()
+{
+	u32 ramcode = ram_code();
+
+	if (ramcode >= ARRAY_SIZE(sdram_configs)
+			|| sdram_configs[ramcode].dramtype == UNUSED)
+		die("Invalid RAMCODE.");
+	return &sdram_configs[ramcode];
+}

src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc

@@ -0,0 +1,77 @@
+{
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		},
+		{
+			.rank = 0x0,
+			.col = 0x0,
+			.bk = 0x0,
+			.bw = 0x0,
+			.dbw = 0x0,
+			.row_3_4 = 0x0,
+			.cs0_row = 0x0,
+			.cs1_row = 0x0
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 2,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 1,
+	.stride = 22,
+	.odt = 1
+},

src/mainboard/google/veyron_rialto/sdram_inf/sdram-unused.inc

@@ -0,0 +1,3 @@
+{
+	.dramtype= UNUSED
+},