- First pass at getting the powerpc ports to compile
The static device tree is not built properly at all yet, but at least we get through it. FIXME (What is the proper way to handle add in boards?) - Add generic div64 support and ppc div64 support - Fix abuild so it properly generates the CC line when cross compiling. - Add one more possible ppc cross compiler target git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
cd51e6ad90
commit
692f2c7aed
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@ -0,0 +1 @@
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#include <arch-generic/div64.h>
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@ -9,12 +9,12 @@ initobject init.c
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driver pci_bridge.c
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arch ppc end
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cpu ppc/ppc4xx end
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chip cpu/ppc/ppc4xx device pnp 0.0 on end end
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##
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## Include the secondary Configuration files
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##
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southbridge winbond/w83c553 end
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chip southbridge/winbond/w83c553 device pnp 0.0 on end end
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##
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## Build the objects we have code for in this directory.
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@ -8,6 +8,41 @@ uses ISA_IO_BASE
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uses ISA_MEM_BASE
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uses TTYS0_BASE
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uses _IO_BASE
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uses CPU_OPT
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uses CROSS_COMPILE
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uses HAVE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses CONFIG_CHIP_CONFIGURE
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD TTYS0_DIV
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uses NO_POST
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uses CONFIG_IDE
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uses CONFIG_FS_STREAM
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uses CONFIG_FS_EXT2
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uses CONFIG_FS_ISO9660
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uses CONFIG_FS_FAT
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uses AUTOBOOT_CMDLINE
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uses CONFIG_SYS_CLK_FREQ
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uses IDE_BOOT_DRIVE
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#uses IDE_SWAB
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uses IDE_OFFSET
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uses ROM_SIZE
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uses _RESET
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uses _EXCEPTION_VECTORS
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uses _ROMBASE
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uses _ROMSTART
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uses _RAMBASE
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#uses _RAMSTART
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uses EMBEDDED_RAM_SIZE
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uses STACK_SIZE HEAP_SIZE
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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@ -33,3 +68,74 @@ default _IO_BASE=ISA_IO_BASE
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##
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default TTYS0_BASE=0xef600300-ISA_IO_BASE
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## Enable PPC405 instructions
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default CPU_OPT="-Wa,-m405"
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default CPU_OPT=""
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## Use stage 1 initialization code
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default CONFIG_USE_INIT=1
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## Use chip configuration
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default CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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default CONFIG_COMPRESS=0
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## Turn off POST codes
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default NO_POST=1
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## Enable serial console
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default DEFAULT_CONSOLE_LOGLEVEL=8
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default CONFIG_CONSOLE_SERIAL8250=1
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# Divisor of 69 == 9600 baud due to weird clocking
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default TTYS0_DIV=69
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default TTYS0_BAUD=9600
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## Boot linux from IDE
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default CONFIG_IDE=1
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default CONFIG_FS_STREAM=1
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default CONFIG_FS_EXT2=1
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default CONFIG_FS_ISO9660=1
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default CONFIG_FS_FAT=1
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default AUTOBOOT_CMDLINE="hda1:/vmlinuz"
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default ROM_SIZE=1048576
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## Board has fixed size RAM
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default EMBEDDED_RAM_SIZE=64*1024*1024
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## LinuxBIOS C code runs at this location in RAM
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default _RAMBASE=0x00100000
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##
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## Use a 64K stack
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##
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default STACK_SIZE=0x10000
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##
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## Use a 64K heap
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##
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default HEAP_SIZE=0x10000
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##
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## System clock
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##
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default CONFIG_SYS_CLK_FREQ=33
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##
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default _ROMBASE=0xfff00000
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## Reset vector address
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default _RESET=0xfffffffc
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## Exception vectors
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default _EXCEPTION_VECTORS=_ROMBASE+0x100
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## linuxBIOS ROM start address
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default _ROMSTART=0xfff03000
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## linuxBIOS C code runs at this location in RAM
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default _RAMBASE=0x00100000
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### End Options.lb
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end
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@ -20,30 +20,30 @@ object clock.o
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arch ppc end
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if CONFIG_SANDPOINT_ALTIMUS
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pmc altimus/mpc7410 end
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# pmc altimus/mpc7400 end
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# pmc altimus/mpc75x end
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chip pmc/altimus/mpc7410 device pnp 0.0 on end end
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# chip pmc/altimus/mpc7400 device pnp 0.0 on end end
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# chip pmc/altimus/mpc75x device pnp 0.0 on end end
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end
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if CONFIG_SANDPOINT_TALUS
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pmc talus/mpc74x end
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pmc talus/mpc603 end
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chip pmc/talus/mpc74x device pnp 0.0 on end end
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chip pmc/talus/mpc603 device pnp 0.0 on end end
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end
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if CONFIG_SANDPOINT_UNITY
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pmc unity/mpc824x end
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chip pmc/unity/mpc824x device pnp 0.0 on end end
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end
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if CONFIG_SANDPOINT_VALIS
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pmc valis/mpc745x end
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chip pmc/valis/mpc745x device pnp 0.0 on end end
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end
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if CONFIG_SANDPOINT_GYRUS
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pmc gyrus/mpc744x end
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chip pmc/gyrus/mpc744x device pnp 0.0 on end end
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end
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##
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## Include the secondary Configuration files
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##
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southbridge winbond/w83c553 end
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chip southbridge/winbond/w83c553 device pnp 0.0 on end end
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superio NSC/pc97307 end
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chip superio/NSC/pc97307 device pnp 0.0 on end end
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##
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## Build the objects we have code for in this directory.
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@ -10,6 +10,39 @@ uses PCIC0_CFGDATA
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uses PNP_CFGADDR
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uses PNP_CFGDATA
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uses _IO_BASE
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uses CROSS_COMPILE
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uses HAVE_OPTION_TABLE
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uses CONFIG_SANDPOINT_ALTIMUS
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uses CONFIG_COMPRESS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses CONFIG_CHIP_CONFIGURE
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uses NO_POST
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BASE
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uses CONFIG_IDE
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uses CONFIG_FS_STREAM
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uses CONFIG_FS_EXT2
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uses CONFIG_FS_ISO9660
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uses CONFIG_FS_FAT
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uses AUTOBOOT_CMDLINE
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uses PAYLOAD_SIZE
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uses ROM_SIZE
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uses ROM_IMAGE_SIZE
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uses _RESET
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uses _EXCEPTION_VECTORS
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uses _ROMBASE
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uses _ROMSTART
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uses _RAMBASE
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uses _RAMSTART
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uses STACK_SIZE
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uses HEAP_SIZE
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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@ -25,3 +58,65 @@ default PCIC0_CFGDATA=0xfee00000
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default PNP_CFGADDR=0x15c
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default PNP_CFGDATA=0x15d
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default _IO_BASE=ISA_IO_BASE
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## use a cross compiler
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#default CROSS_COMPILE="powerpc-eabi-"
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#default CROSS_COMPILE="ppc_74xx-"
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## Use stage 1 initialization code
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default CONFIG_USE_INIT=1
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## Use static configuration
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default CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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default CONFIG_COMPRESS=0
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## Turn off POST codes
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default NO_POST=1
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## Enable serial console
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default DEFAULT_CONSOLE_LOGLEVEL=8
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default CONFIG_CONSOLE_SERIAL8250=1
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default TTYS0_BASE=0x3f8
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## Load payload using filo
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default CONFIG_IDE=1
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default CONFIG_FS_STREAM=1
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default CONFIG_FS_EXT2=1
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default CONFIG_FS_ISO9660=1
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default CONFIG_FS_FAT=1
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default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
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# LinuxBIOS must fit into 128KB
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default ROM_IMAGE_SIZE=131072
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default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
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default PAYLOAD_SIZE=262144
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# Set stack and heap sizes (stage 2)
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default STACK_SIZE=0x10000
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default HEAP_SIZE=0x10000
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# Sandpoint Demo Board
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## Base of ROM
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default _ROMBASE=0xfff00000
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## Sandpoint reset vector
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default _RESET=_ROMBASE+0x100
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## Exception vectors (other than reset vector)
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default _EXCEPTION_VECTORS=_RESET+0x100
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## Start of linuxBIOS in the boot rom
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## = _RESET + exeception vector table size
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default _ROMSTART=_RESET+0x3100
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## LinuxBIOS C code runs at this location in RAM
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default _RAMBASE=0x00100000
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default _RAMSTART=0x00100000
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default CONFIG_SANDPOINT_ALTIMUS=1
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### End Options.lb
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end
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@ -16,17 +16,17 @@ object clock.o
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arch ppc end
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if CONFIG_BRIQ_750FX
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cpu ppc/ppc7xx end
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chip cpu/ppc/ppc7xx device pnp 0.0 on end end
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end
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if CONFIG_BRIQ_7400
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cpu ppc/mpc74xx end
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chip cpu/ppc/mpc74xx device pnp 0.0 on end end
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end
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##
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## Include the secondary Configuration files
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##
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northbridge ibm/cpc710 end
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southbridge winbond/w83c553 end
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chip northbridge/ibm/cpc710 device pnp 0.0 on end end
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chip southbridge/winbond/w83c553 device pnp 0.0 on end end
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##
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## Build the objects we have code for in this directory.
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@ -11,6 +11,32 @@ uses ISA_MEM_BASE
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uses PCIC0_CFGADDR
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uses PCIC0_CFGDATA
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uses _IO_BASE
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uses CROSS_COMPILE
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uses HAVE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses NO_POST
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_IDE_STREAM
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uses IDE_BOOT_DRIVE
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uses IDE_SWAB IDE_OFFSET
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uses ROM_SIZE
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uses _RESET
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uses _EXCEPTION_VECTORS
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uses _ROMBASE
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uses _ROMSTART
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uses _RAMBASE
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uses _RAMSTART
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uses STACK_SIZE
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uses HEAP_SIZE
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uses CONFIG_BRIQ_750FX
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uses CONFIG_BRIQ_7400
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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@ -33,3 +59,57 @@ default TTYS0_DIV=4
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## Set UART base address
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##
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default TTYS0_BASE=0x3f8
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## use a cross compiler
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#default CROSS_COMPILE="powerpc-eabi-"
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#default CROSS_COMPILE="ppc_74xx-"
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## Use stage 1 initialization code
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default CONFIG_USE_INIT=1
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## We don't use compressed image
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default CONFIG_COMPRESS=0
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## Turn off POST codes
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default NO_POST=1
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## Enable serial console
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default DEFAULT_CONSOLE_LOGLEVEL=8
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default CONFIG_CONSOLE_SERIAL8250=1
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## Boot linux from IDE
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default CONFIG_IDE_STREAM=1
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default IDE_BOOT_DRIVE=0
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default IDE_SWAB=1
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default IDE_OFFSET=0
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# ROM is 1Mb
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default ROM_SIZE=1048576
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# Set stack and heap sizes (stage 2)
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default STACK_SIZE=0x10000
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default HEAP_SIZE=0x10000
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# Sandpoint Demo Board
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## Base of ROM
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default _ROMBASE=0xfff00000
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## Sandpoint reset vector
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default _RESET=_ROMBASE+0x100
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## Exception vectors (other than reset vector)
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default _EXCEPTION_VECTORS=_RESET+0x100
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## Start of linuxBIOS in the boot rom
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## = _RESET + exeception vector table size
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default _ROMSTART=_RESET+0x3100
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## LinuxBIOS C code runs at this location in RAM
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default _RAMBASE=0x00100000
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default _RAMSTART=0x00100000
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default CONFIG_BRIQ_750FX=1
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#default CONFIG_BRIQ_7400=1
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### End Options.lb
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end
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|
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@ -1,12 +1,12 @@
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##
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## CPU initialization
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##
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cpu ppc/mpc74xx end
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chip cpu/ppc/mpc74xx device pnp 0.0 on end end
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##
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## Include the secondary Configuration files
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##
|
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northbridge motorola/mpc107 end
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chip northbridge/motorola/mpc107 device pnp 0.0 on end end
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##
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## Build the objects we have code for in this directory.
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|
|
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@ -34,7 +34,7 @@ function debug
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{
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test "$verbose" == "true" && echo $*
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}
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function vendors
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{
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# make this a function so we can easily select
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@ -64,6 +64,7 @@ function create_config
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{
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VENDOR=$1
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MAINBOARD=$2
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TARCH=$( architecture $VENDOR $MAINBOARD )
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echo -n " Creating config file..."
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mkdir -p $TARGET
|
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( cat << EOF
|
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|
|
@ -76,6 +77,9 @@ option CC="CROSSCC"
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option CROSS_COMPILE="CROSS_PREFIX"
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option HOSTCC="CROSS_HOSTCC"
|
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|
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EOF
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if [ $TARCH == i386 ] ; then
|
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cat <<EOF
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romimage "normal"
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option USE_FALLBACK_IMAGE=0
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option ROM_IMAGE_SIZE=0x12000
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|
|
@ -89,9 +93,17 @@ romimage "fallback"
|
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option LINUXBIOS_EXTRA_VERSION=".0-fallback"
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payload PAYLOAD
|
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end
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buildrom ./VENDOR_MAINBOARD.rom ROM_SIZE "normal" "fallback"
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buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
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EOF
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else
|
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cat <<EOF
|
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romimage "only"
|
||||
option LINUXBIOS_EXTRA_VERSION=".0"
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payload PAYLOAD
|
||||
end
|
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buildrom ./linuxbios.rom ROM_SIZE "only"
|
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EOF
|
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fi
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) | sed -e s,VENDOR,$VENDOR,g \
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-e s,MAINBOARD,$MAINBOARD,g \
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-e s,PAYLOAD,$PAYLOAD,g \
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|
|
@ -199,9 +211,9 @@ function build_target
|
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TARCH=$( architecture $VENDOR $MAINBOARD )
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|
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# default setting
|
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CC="gcc"
|
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HOSTCC="gcc"
|
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CROSS_COMPILE=""
|
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CC='$(CROSS_COMPILE)gcc'
|
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HOSTCC='gcc'
|
||||
CROSS_COMPILE=''
|
||||
|
||||
echo -n "Processing mainboard/$VENDOR/$MAINBOARD"
|
||||
|
||||
|
|
@ -218,7 +230,7 @@ function build_target
|
|||
found_crosscompiler=true
|
||||
fi
|
||||
if [ "$found_crosscompiler" == "false" -a "$TARCH" == ppc ] ;then
|
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for prefix in powerpc-eabi- powerpc-linux- ; do
|
||||
for prefix in powerpc-eabi- powerpc-linux- ppc_74xx- ; do
|
||||
if ${prefix}gcc --version > /dev/null 2> /dev/null ; then
|
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found_crosscompiler=true
|
||||
CROSS_COMPILE=$prefix
|
||||
|
|
@ -235,17 +247,17 @@ function build_target
|
|||
echo
|
||||
return 0
|
||||
else
|
||||
echo " ($TARCH: ok, though we're $ARCH)"
|
||||
echo " ($TARCH: ok, we're $ARCH)"
|
||||
fi
|
||||
fi
|
||||
|
||||
|
||||
built_successfully $VENDOR $MAINBOARD && \
|
||||
{
|
||||
echo " ( mainboard/$VENDOR/$MAINBOARD previously ok )"
|
||||
echo
|
||||
return 0
|
||||
}
|
||||
|
||||
|
||||
build_broken $VENDOR $MAINBOARD || \
|
||||
{
|
||||
echo " ( broken mainboard/$VENDOR/$MAINBOARD skipped )"
|
||||
|
|
@ -313,7 +325,7 @@ while true ; do
|
|||
case "$1" in
|
||||
-t|--target) shift; target="$1"; shift;;
|
||||
-a|--all) shift; buildall=true;;
|
||||
-b|--broken) shift; buildbroken=true;;
|
||||
-b|--broken) shift; buildbroken=true;;
|
||||
-v|--verbose) shift; verbose=true;;
|
||||
-V|--version) shift; myversion; exit 0;;
|
||||
-h|--help) shift; myhelp; exit 0;;
|
||||
|
|
@ -323,6 +335,7 @@ while true ; do
|
|||
esac
|
||||
done
|
||||
|
||||
# /path/to/freebios2/
|
||||
test -z "$1" || LBROOT=$1
|
||||
|
||||
debug "LBROOT=$LBROOT"
|
||||
|
|
|
|||
Loading…
Reference in New Issue