mb/google/rex: Enable stylus support

This patch enables stylus support by configuring the "GPP_D08" irqs for
rex SoC. This allows the SoC to detect a stylus device, when in use.
However stylus is not a wake up source for the rex.

BUG=b:282256460
Test=Stylus is detected on proto1 device.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Dinesh Gehlot 2023-01-11 06:50:37 +00:00 committed by Jakub Czapiga
parent 141d0dfafb
commit 6930b9580e
3 changed files with 13 additions and 2 deletions

View File

@ -33,6 +33,7 @@ config BOARD_GOOGLE_BASEBOARD_REX
def_bool n
select BOARD_GOOGLE_REX_COMMON
select DRIVERS_INTEL_PMC
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_WWAN_FM350GL
select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
select HAVE_SLP_S0_GATE

View File

@ -198,8 +198,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG),
/* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_E04 : [] ==> HPS_INT_L */
PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, NONE),
/* GPP_E04 : [] ==> PEN_DETECT */
PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */
PAD_CFG_GPO(GPP_E05, 1, DEEP),
/* GPP_E06 : GPP_E06_STRAP ==> Component NC */

View File

@ -533,6 +533,16 @@ chip soc/intel/meteorlake
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
# GPP_E04 is the IRQ source
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E04)"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""pen_eject""
device generic 0 on end
end
end
device ref i2c2 on end
device ref i2c3 on