soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design BUG=b:184653645 BRANCH=None TEST=compilation works fine and value of UPD is getting reflected. Change-Id: I61faa661c12dced27c6cdd7005a61ae8de8621e1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
parent
ba0ab9f1f5
commit
6935350ad6
|
@ -9,6 +9,7 @@
|
||||||
#include <intelblocks/gspi.h>
|
#include <intelblocks/gspi.h>
|
||||||
#include <intelblocks/power_limit.h>
|
#include <intelblocks/power_limit.h>
|
||||||
#include <intelblocks/pcie_rp.h>
|
#include <intelblocks/pcie_rp.h>
|
||||||
|
#include <intelblocks/tcss.h>
|
||||||
#include <soc/gpe.h>
|
#include <soc/gpe.h>
|
||||||
#include <soc/pci_devs.h>
|
#include <soc/pci_devs.h>
|
||||||
#include <soc/pmc.h>
|
#include <soc/pmc.h>
|
||||||
|
@ -87,6 +88,8 @@ struct soc_intel_alderlake_config {
|
||||||
uint16_t usb2_wake_enable_bitmap;
|
uint16_t usb2_wake_enable_bitmap;
|
||||||
/* Wake Enable Bitmap for USB3 ports */
|
/* Wake Enable Bitmap for USB3 ports */
|
||||||
uint16_t usb3_wake_enable_bitmap;
|
uint16_t usb3_wake_enable_bitmap;
|
||||||
|
/* Program OC pins for TCSS */
|
||||||
|
struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
|
||||||
|
|
||||||
/* SATA related */
|
/* SATA related */
|
||||||
uint8_t SataEnable;
|
uint8_t SataEnable;
|
||||||
|
|
|
@ -184,6 +184,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
|
||||||
|
if (config->tcss_ports[i].enable)
|
||||||
|
params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
|
||||||
|
}
|
||||||
|
|
||||||
/* Enable xDCI controller if enabled in devicetree and allowed */
|
/* Enable xDCI controller if enabled in devicetree and allowed */
|
||||||
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
|
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
|
||||||
if (dev) {
|
if (dev) {
|
||||||
|
|
|
@ -135,4 +135,20 @@ struct usb3_port_config {
|
||||||
.tx_downscale_amp = 0x00, \
|
.tx_downscale_amp = 0x00, \
|
||||||
}
|
}
|
||||||
|
|
||||||
|
struct tcss_port_config {
|
||||||
|
uint8_t enable;
|
||||||
|
uint8_t ocpin;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define TCSS_PORT_EMPTY { \
|
||||||
|
.enable = 0, \
|
||||||
|
.ocpin = OC_SKIP, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define TCSS_PORT_DEFAULT(pin) { \
|
||||||
|
.enable = 1, \
|
||||||
|
.ocpin = (pin), \
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in New Issue