soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design BUG=b:184653645 BRANCH=None TEST=compilation works fine and value of UPD is getting reflected. Change-Id: I61faa661c12dced27c6cdd7005a61ae8de8621e1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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@ -9,6 +9,7 @@
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#include <intelblocks/gspi.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/pcie_rp.h>
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#include <intelblocks/tcss.h>
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#include <soc/gpe.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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@ -87,6 +88,8 @@ struct soc_intel_alderlake_config {
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uint16_t usb2_wake_enable_bitmap;
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/* Wake Enable Bitmap for USB3 ports */
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uint16_t usb3_wake_enable_bitmap;
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/* Program OC pins for TCSS */
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struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
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/* SATA related */
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uint8_t SataEnable;
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@ -184,6 +184,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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}
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}
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for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
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if (config->tcss_ports[i].enable)
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params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
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}
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
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if (dev) {
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@ -135,4 +135,20 @@ struct usb3_port_config {
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.tx_downscale_amp = 0x00, \
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}
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struct tcss_port_config {
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uint8_t enable;
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uint8_t ocpin;
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};
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#define TCSS_PORT_EMPTY { \
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.enable = 0, \
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.ocpin = OC_SKIP, \
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}
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#define TCSS_PORT_DEFAULT(pin) { \
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.enable = 1, \
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.ocpin = (pin), \
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}
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#endif
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