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nb/intel/pineview: Use MiB definition

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Also constify a local variable while we're at it.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-08-03 15:16:12 +02:00
parent 92e4ca6a38
commit 69356489fe
3 changed files with 10 additions and 9 deletions
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4
src/northbridge/intel/pineview/acpi.c
View file

@ -2,6 +2,7 @@
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <commonlib/helpers.h>
#include <device/device.h> #include <device/device.h>
#include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/pineview.h>
#include <types.h> #include <types.h>
@ -9,12 +10,11 @@
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {
u32 length, pciexbar; u32 length, pciexbar;
int max_buses;
if (!decode_pciebar(&pciexbar, &length)) if (!decode_pciebar(&pciexbar, &length))
return current; return current;
max_buses = length >> 20; const int max_buses = length / MiB;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
max_buses - 1); max_buses - 1);

9
src/northbridge/intel/pineview/memmap.c
View file

@ -3,6 +3,7 @@
#define __SIMPLE_DEVICE__ #define __SIMPLE_DEVICE__
#include <arch/romstage.h> #include <arch/romstage.h>
#include <commonlib/helpers.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -51,7 +52,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
} }
*base = pciexbar; *base = pciexbar;
*len = max_buses << 20; *len = max_buses * MiB;
return 1; return 1;
} }
@ -87,11 +88,11 @@ static u32 decode_tseg_size(const u32 esmramc)
switch ((esmramc >> 1) & 3) { switch ((esmramc >> 1) & 3) {
case 0: case 0:
return 1 << 20; return 1 * MiB;
case 1: case 1:
return 2 << 20; return 2 * MiB;
case 2: case 2:
return 8 << 20; return 8 * MiB;
case 3: case 3:
default: default:
die("Bad TSEG setting.\n"); die("Bad TSEG setting.\n");

6
src/northbridge/intel/pineview/northbridge.c
View file

@ -18,7 +18,7 @@
* 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
* 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
*/ */
static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_base_k = 0xa0000 / KiB;
static void add_fixed_resources(struct device *dev, int index) static void add_fixed_resources(struct device *dev, int index)
{ {
@ -33,8 +33,8 @@ static void add_fixed_resources(struct device *dev, int index)
| IORESOURCE_STORED | IORESOURCE_STORED
| IORESOURCE_ASSIGNED; | IORESOURCE_ASSIGNED;
mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
} }
static void mch_domain_read_resources(struct device *dev) static void mch_domain_read_resources(struct device *dev)