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pcengines/apu2: enable IOMMU for all apu2 variants 

IOMMU was tested on Xen 4.8 and Linux kernel 4.14.33. Following feature
set is enabled:
(XEN) AMD-Vi: Disabled HAP memory map sharing with IOMMU
(XEN) AMD-Vi: IOMMU Extended Features:
(XEN)  - Peripheral Page Service Request
(XEN)  - Guest Translation
(XEN)  - Invalidate All Command
(XEN)  - Guest APIC supported
(XEN)  - Performance Counters
(XEN) AMD-Vi: IOMMU 0 Enabled.

Change-Id: I6dbfae78849248f3532caa78974c8f2ce61a530d
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/26116
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Piotr Król 2018-05-04 17:40:11 +02:00 committed by Patrick Georgi
parent 9ef07d8623
commit 694d18a641
4 changed files with 4 additions and 4 deletions
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2
src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
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@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge device pci 2.0 on end # PCIe Host Bridge

2
src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
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@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge device pci 2.0 on end # PCIe Host Bridge

2
src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
View File

@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge device pci 2.0 on end # PCIe Host Bridge

2
src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
View File

@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge device pci 2.0 on end # PCIe Host Bridge