soc/intel/jasperlake: Disable PAVP UPD

This patch will disable PAVP UPD, which is by default enabled in FSP.

BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD values from FSP log

Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41763
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ronak Kanabar 2020-05-27 11:25:45 +05:30 committed by Patrick Georgi
parent 316c180c41
commit 69589294c2
1 changed files with 3 additions and 0 deletions

View File

@ -210,6 +210,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->XdciEnable = 0;
}
/* Disable Pavp */
params->PavpEnable = 0;
/* Provide correct UART number for FSP debug logs */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;