soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR

This makes coreboot more robust as it does not need to rely on syncing
values set by FSP and coreboot.

Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47533
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/xeon_sp/Kconfig

@@ -49,6 +49,7 @@ config	CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
 	select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_P2SB
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select SUPPORT_CPU_UCODE_IN_CBFS

src/soc/intel/xeon_sp/nb_acpi.c

@@ -12,6 +12,7 @@
 #include <soc/pci_devs.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
+#include <intelblocks/p2sb.h>
 
 #include "chip.h"
 
@@ -267,11 +268,12 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket,
 		//BIT 15
 		if (num_hpets && (num_hpets != 0x1f) &&
 			(read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) {
+			union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf();
 			printk(BIOS_DEBUG, "    [Message-capable HPET Device] Enumeration ID: 0x%x, "
 				"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
-				0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM);
+				0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn);
-			current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM,
+			current += acpi_create_dmar_ds_msi_hpet(current, 0, hpet_bdf.bus,
-				HPET_DEV_NUM, HPET0_FUNC_NUM);
+				hpet_bdf.dev, hpet_bdf.fn);
 		}
 	}