Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.
The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but Browell supports up to 4 ports, so we need to support setting IOBP for ports 2 and 3 as well. The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only guessed by looking at ports 0 and 1 and extrapolating from there. Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work so we can assume that port 2 and 3 magic numbers are valid, but having someone confirm them (through non-public documents?) would be great. Change-Id: I59911cfa677749ceea9a544a99b444722392e72d Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18408 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -44,8 +44,12 @@ struct soc_intel_broadwell_config {
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uint8_t sata_port_map;
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uint32_t sata_port0_gen3_tx;
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uint32_t sata_port1_gen3_tx;
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uint32_t sata_port2_gen3_tx;
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uint32_t sata_port3_gen3_tx;
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uint32_t sata_port0_gen3_dtle;
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uint32_t sata_port1_gen3_dtle;
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uint32_t sata_port2_gen3_dtle;
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uint32_t sata_port3_gen3_dtle;
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/*
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* SATA DEVSLP Mux
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@ -23,6 +23,8 @@
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/* SATA IOBP Registers */
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#define SATA_IOBP_SP0_SECRT88 0xea002688
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#define SATA_IOBP_SP1_SECRT88 0xea002488
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#define SATA_IOBP_SP2_SECRT88 0xea002288
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#define SATA_IOBP_SP3_SECRT88 0xea002088
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#define SATA_SECRT88_VADJ_MASK 0xff
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#define SATA_SECRT88_VADJ_SHIFT 16
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@ -31,6 +33,10 @@
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#define SATA_IOBP_SP0DTLE_EDGE 0xea002754
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#define SATA_IOBP_SP1DTLE_DATA 0xea002550
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#define SATA_IOBP_SP1DTLE_EDGE 0xea002554
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#define SATA_IOBP_SP2DTLE_DATA 0xea002350
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#define SATA_IOBP_SP2DTLE_EDGE 0xea002354
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#define SATA_IOBP_SP3DTLE_DATA 0xea002150
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#define SATA_IOBP_SP3DTLE_EDGE 0xea002154
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#define SATA_DTLE_MASK 0xF
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#define SATA_DTLE_DATA_SHIFT 24
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@ -149,6 +149,22 @@ static void sata_init(struct device *dev)
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SATA_SECRT88_VADJ_MASK)
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<< SATA_SECRT88_VADJ_SHIFT);
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if (config->sata_port2_gen3_tx)
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pch_iobp_update(SATA_IOBP_SP2_SECRT88,
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~(SATA_SECRT88_VADJ_MASK <<
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SATA_SECRT88_VADJ_SHIFT),
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(config->sata_port2_gen3_tx &
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SATA_SECRT88_VADJ_MASK)
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<< SATA_SECRT88_VADJ_SHIFT);
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if (config->sata_port3_gen3_tx)
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pch_iobp_update(SATA_IOBP_SP3_SECRT88,
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~(SATA_SECRT88_VADJ_MASK <<
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SATA_SECRT88_VADJ_SHIFT),
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(config->sata_port2_gen3_tx &
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SATA_SECRT88_VADJ_MASK)
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<< SATA_SECRT88_VADJ_SHIFT);
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/* Set Gen3 DTLE DATA / EDGE registers if needed */
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if (config->sata_port0_gen3_dtle) {
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pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
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@ -174,6 +190,30 @@ static void sata_init(struct device *dev)
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<< SATA_DTLE_EDGE_SHIFT);
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}
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if (config->sata_port2_gen3_dtle) {
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pch_iobp_update(SATA_IOBP_SP2DTLE_DATA,
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~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
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(config->sata_port2_gen3_dtle & SATA_DTLE_MASK)
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<< SATA_DTLE_DATA_SHIFT);
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pch_iobp_update(SATA_IOBP_SP2DTLE_EDGE,
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~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
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(config->sata_port2_gen3_dtle & SATA_DTLE_MASK)
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<< SATA_DTLE_EDGE_SHIFT);
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}
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if (config->sata_port3_gen3_dtle) {
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pch_iobp_update(SATA_IOBP_SP3DTLE_DATA,
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~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
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(config->sata_port3_gen3_dtle & SATA_DTLE_MASK)
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<< SATA_DTLE_DATA_SHIFT);
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pch_iobp_update(SATA_IOBP_SP3DTLE_EDGE,
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~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
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(config->sata_port3_gen3_dtle & SATA_DTLE_MASK)
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<< SATA_DTLE_EDGE_SHIFT);
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}
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/*
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* Additional Programming Requirements for Power Optimizer
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*/
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