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Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3. 

The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but
Browell supports up to 4 ports, so we need to support setting IOBP for
ports 2 and 3 as well.
The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only
guessed by looking at ports 0 and 1 and extrapolating from there.
Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work
so we can assume that port 2 and 3 magic numbers are valid, but having
someone confirm them (through non-public documents?) would be great.

Change-Id: I59911cfa677749ceea9a544a99b444722392e72d
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18408
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Youness Alaoui 2017-02-07 13:54:45 -05:00 committed by Martin Roth
parent c0ebe4a751
commit 696ebc2dbc
3 changed files with 50 additions and 0 deletions
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4
src/soc/intel/broadwell/chip.h
View File

@ -44,8 +44,12 @@ struct soc_intel_broadwell_config {
uint8_t sata_port_map;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
uint32_t sata_port2_gen3_tx;
uint32_t sata_port3_gen3_tx;
uint32_t sata_port0_gen3_dtle;
uint32_t sata_port1_gen3_dtle;
uint32_t sata_port2_gen3_dtle;
uint32_t sata_port3_gen3_dtle;
/*
* SATA DEVSLP Mux

6
src/soc/intel/broadwell/include/soc/sata.h
View File

@ -23,6 +23,8 @@
/* SATA IOBP Registers */
#define SATA_IOBP_SP0_SECRT88 0xea002688
#define SATA_IOBP_SP1_SECRT88 0xea002488
#define SATA_IOBP_SP2_SECRT88 0xea002288
#define SATA_IOBP_SP3_SECRT88 0xea002088
#define SATA_SECRT88_VADJ_MASK 0xff
#define SATA_SECRT88_VADJ_SHIFT 16
@ -31,6 +33,10 @@
#define SATA_IOBP_SP0DTLE_EDGE 0xea002754
#define SATA_IOBP_SP1DTLE_DATA 0xea002550
#define SATA_IOBP_SP1DTLE_EDGE 0xea002554
#define SATA_IOBP_SP2DTLE_DATA 0xea002350
#define SATA_IOBP_SP2DTLE_EDGE 0xea002354
#define SATA_IOBP_SP3DTLE_DATA 0xea002150
#define SATA_IOBP_SP3DTLE_EDGE 0xea002154
#define SATA_DTLE_MASK 0xF
#define SATA_DTLE_DATA_SHIFT 24

40
src/soc/intel/broadwell/sata.c
View File

@ -149,6 +149,22 @@ static void sata_init(struct device *dev)
SATA_SECRT88_VADJ_MASK)
<< SATA_SECRT88_VADJ_SHIFT);
if (config->sata_port2_gen3_tx)
pch_iobp_update(SATA_IOBP_SP2_SECRT88,
~(SATA_SECRT88_VADJ_MASK <<
SATA_SECRT88_VADJ_SHIFT),
(config->sata_port2_gen3_tx &
SATA_SECRT88_VADJ_MASK)
<< SATA_SECRT88_VADJ_SHIFT);
if (config->sata_port3_gen3_tx)
pch_iobp_update(SATA_IOBP_SP3_SECRT88,
~(SATA_SECRT88_VADJ_MASK <<
SATA_SECRT88_VADJ_SHIFT),
(config->sata_port2_gen3_tx &
SATA_SECRT88_VADJ_MASK)
<< SATA_SECRT88_VADJ_SHIFT);
/* Set Gen3 DTLE DATA / EDGE registers if needed */
if (config->sata_port0_gen3_dtle) {
pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
@ -174,6 +190,30 @@ static void sata_init(struct device *dev)
<< SATA_DTLE_EDGE_SHIFT);
}
if (config->sata_port2_gen3_dtle) {
pch_iobp_update(SATA_IOBP_SP2DTLE_DATA,
~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
(config->sata_port2_gen3_dtle & SATA_DTLE_MASK)
<< SATA_DTLE_DATA_SHIFT);
pch_iobp_update(SATA_IOBP_SP2DTLE_EDGE,
~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
(config->sata_port2_gen3_dtle & SATA_DTLE_MASK)
<< SATA_DTLE_EDGE_SHIFT);
}
if (config->sata_port3_gen3_dtle) {
pch_iobp_update(SATA_IOBP_SP3DTLE_DATA,
~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
(config->sata_port3_gen3_dtle & SATA_DTLE_MASK)
<< SATA_DTLE_DATA_SHIFT);
pch_iobp_update(SATA_IOBP_SP3DTLE_EDGE,
~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
(config->sata_port3_gen3_dtle & SATA_DTLE_MASK)
<< SATA_DTLE_EDGE_SHIFT);
}
/*
* Additional Programming Requirements for Power Optimizer
*/